Low CTE Substrate Cavities for Multi-Wiring Interconnects
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Solution Overview
Problem
Microelectronic devices face challenges with stress in substrates due to thermal expansion, which existing methods have not adequately addressed, particularly in designs involving electrical connections and interconnections between chips and substrates.
Innovation Solution
An interconnection component with conductors extending through an opening between surfaces, featuring a low coefficient of thermal expansion material, dielectric layers, and wettable contacts, along with bond materials, to minimize stress and enhance electrical insulation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional substrates with standard CTE materials are used for electrical interconnections, then electrical connectivity is achieved, but high stress is generated in the substrate due to thermal expansion mismatch
Solution Approach 1:
The patent changes the CTE parameter of the substrate material by using low CTE materials (such as ceramic substrates with CTE of 5-15 ppm/°C) instead of conventional organic substrates. This parameter change allows the substrate to better match the thermal expansion characteristics of the electrical components, thereby reducing thermal stress while maintaining electrical connectivity through conductive vias and traces
Solution Approach 2:
The patent employs composite material structures combining low CTE ceramic substrates with conductive metal traces and vias. The ceramic matrix provides low thermal expansion, while embedded metal conductors provide electrical connectivity. This composite approach resolves the contradiction by decoupling the thermal expansion properties from the electrical conductivity properties
2Reliability
If through-substrate vias are used to provide electrical interconnection between chips, then electrical connectivity is improved, but stress concentration and potential substrate failure increase
Solution Approach 1:
The patent applies stress relief structures such as compliance features, stress equalization layers, and flexible interconnect designs in advance of thermal cycling. These features are built into the substrate structure before operation to cushion against thermal stress, preventing via failure and maintaining electrical interconnection reliability under thermal expansion/contraction cycles
Solution Approach 2:
The patent incorporates flexible stress equalization layers and compliant interconnect structures that can deform elastically during thermal cycling. These thin film or layered structures accommodate dimensional changes without generating excessive stress concentrations at via locations, thereby protecting the substrate strength while maintaining electrical connectivity
3Reliability
If area array contact patterns are used to cover the device surface, then electrical connectivity is enhanced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs the substrate and contact structures to serve multiple functions: the low CTE substrate provides both mechanical support and thermal stability, the conductive traces provide both electrical connection and stress distribution, and the contact pads serve both electrical interconnection and alignment reference functions. This multi-functionality reduces overall device complexity while maintaining enhanced electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress in substrates by using low CTE materials and dielectric insulation, improving electrical connectivity and reliability of microelectronic devices while maintaining signal integrity and reducing unwanted effects like cross-talk.
Implementation Method 1
thermal expansion between the material comprising the via and the surrounding material of the substrate itself can lead to a high degree of stress in the substrate
Implementation Method 2
The plurality of conductors that extend through the opening are electrically insulated from one another
Data Source
AI summary
A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.