Low CTE Component Wire Bond Interconnects
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Solution Overview
Problem
The existing methods for forming through-silicon vias (TSVs) in semiconductor elements with low coefficient of thermal expansion (CTE) materials are costly and challenging due to the need for thinning wafers and filling high aspect ratio holes with deposited metal, which complicates handling and increases costs.
Innovation Solution
The method involves forming wire bonds as vertical interconnects within openings in a low CTE element, allowing for increased thickness beyond what is possible with TSV processes, eliminating the need for metal deposition in small holes and reducing the requirement for wafer thinning, and enabling thicker low CTE components with wire bonds extending up to 1 millimeter in thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via (TSV) processes are used to form vertical interconnects in low CTE elements, then electrical connection is achieved, but fabrication cost increases and manufacturing complexity increases due to metal deposition in high aspect ratio holes
Solution Approach 1:
The patent extracts the metal deposition step from the TSV formation process by using wire bonds instead of deposited metal fills. Wire bonds are formed by bonding metal wire to contact surfaces, eliminating the need for complex metal deposition processes in high aspect ratio holes, thereby reducing fabrication cost and manufacturing complexity while maintaining electrical connection reliability
Solution Approach 2:
Instead of filling holes with deposited metal (conventional TSV approach), the patent inverts the approach by inserting pre-formed wire bonds into the holes. This inversion simplifies the manufacturing process by replacing complex deposition processes with simpler wire bonding operations, reducing fabrication cost while achieving the same electrical interconnection function
2Length of moving object
If wafer thinning is performed to enable TSV formation, then vertical interconnects can be formed, but handling difficulty increases and manufacturing complexity increases
Solution Approach 1:
The patent performs wire bond formation as a preliminary action before wafer thinning. By forming wire bonds on the thickest practical wafer first, then thinning the wafer afterward, the process avoids the handling difficulties of thin wafers during the critical wire bonding operation. This preliminary action sequence eliminates the need to handle and process extremely thin wafers, reducing manufacturing complexity and handling difficulty
Solution Approach 2:
The patent implements a periodic sequence of operations: first form wire bonds on thick wafers, then thin the wafers, and finally complete the interconnect structure. This periodic action breaks the manufacturing process into manageable stages, avoiding the continuous handling of thin wafers and reducing overall manufacturing complexity while achieving the required element thickness
3Length of stationary object
If element thickness is increased beyond TSV process capabilities, then warpage issues are reduced and thermal expansion management is improved, but electrical interconnection becomes more difficult with conventional TSV methods
Solution Approach 1:
The patent changes the interconnection method parameter from deposited metal fills to wire bonds. This parameter change enables the formation of reliable electrical interconnects in elements of any thickness, as wire bonds can be formed by bonding to contact surfaces without requiring the element to be thinned to specific thickness ranges. This resolves the contradiction by making interconnection difficulty independent of element thickness
Solution Approach 2:
The wire bond interconnection method provides universality by working effectively across a wide range of element thicknesses. Unlike TSV processes that require specific thickness ranges for successful metal deposition and via formation, wire bonds can be formed on elements of any practical thickness, making the interconnection method universally applicable and eliminating the contradiction between thickness and interconnection difficulty
Data Source
AI summary
A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.