Low-Current Comparator Hysteresis Using Intrinsic Latch Capacitance

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Solution Overview

Problem

Conventional comparators fail to operate effectively at very low operational currents (e.g., 100 nA) while maintaining hysteresis, as linear preamplifier stages are not suitable in such conditions.

Innovation Solution

A low current comparator with programmable hysteresis is developed, utilizing a ratio of latch intrinsic capacitance and sampling capacitor capacitance to adjust hysteresis, employing a switch capacitor sampling stage coupled with a dynamic latch output stage, where hysteresis is generated by adding or subtracting charge based on the comparator's output state, without requiring additional capacitors or logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If linear preamplifier stages are used in conventional comparators, then hysteresis can be maintained, but operation at very low currents (e.g., 100 nA) becomes impossible

Engineering Contradiction:
Improveoperational currentVSAvoidhysteresis function
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent extracts the hysteresis generation function from the linear preamplifier stage and relocates it to the dynamic latch stage. By using the latch's intrinsic capacitance to generate hysteresis feedback, the design eliminates the need for linear preamplifier stages that consume excessive current, enabling operation at very low currents while maintaining hysteresis functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dynamic latch stage uses its own intrinsic capacitance (CL) to generate hysteresis, rather than requiring external preamplifier circuits. The latch serves dual purposes: signal latching and hysteresis generation, making the system self-sufficient and eliminating additional current-consuming components.

Inventive Principle:
Principle #25Self-service

2Reliability

If additional capacitors or logic are added to generate hysteresis, then hysteresis function is improved, but device complexity increases

Engineering Contradiction:
Improvehysteresis functionVSAvoidnumber of components
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dynamic latch stage is designed to perform multiple functions simultaneously: signal latching and hysteresis generation. By making the latch multi-functional, the patent eliminates the need for separate hysteresis-generating components such as additional capacitors or logic circuits, thereby reducing device complexity while maintaining robust hysteresis functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the hysteresis generation function with the existing dynamic latch structure. The latch's intrinsic capacitance is utilized for both its primary latching function and for generating hysteresis feedback, consolidating multiple functions into a single component and avoiding additional circuitry.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for adjustable hysteresis without additional components, enabling efficient operation at low currents, thereby addressing the limitations of conventional comparators in low power applications.

Implementation Method 1

hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8198920B2Low current comparator with programmable hysteresis
Publication Date: 2012.06.12 ATMEL CORP
  • US8198920B2 patent drawing
  • US8198920B2 patent drawing
  • US8198920B2 patent drawing

AI summary

A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state (0 or 1) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor. The ratio of latch intrinsic capacitance and the capacitance of the sampling capacitor can be adjusted to trim hysteresis value. The hysteresis function does not require additional capacitors or additional logic.