Low-Current EEPROM Array with Symmetric Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional EEPROM architectures are inefficient due to their large area occupancy and high cost, as they require erasing or programming of memory blocks rather than individual bits, and involve high current consumption during operations.
Innovation Solution
A low-current EEPROM array design with parallel bit lines, word lines, and common source lines, where memory cells are symmetrically arranged to reduce area and cost, and specific voltage applications are used for low-current, low-voltage byte writing and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional EEPROM architecture is used, then byte writing and erasing functions are supported, but current consumption is high and area occupancy is large
Solution Approach 1:
The bit lines are divided into multiple bit line groups (first bit line group, second bit line group, etc.), each connected to specific memory cells. This segmentation allows selective activation of only the bit line groups needed for current operations, reducing overall current consumption while maintaining byte write and erase capabilities.
Solution Approach 2:
The patent introduces a third dimension to the conventional memory array by adding common source lines that extend in a direction perpendicular to both bit lines and word lines. This creates a three-dimensional routing structure that reduces area occupancy while maintaining electrical connectivity for all memory cells.
2Reliability
If conventional EEPROM architecture is used, then non-volatile storage is achieved, but cost increases due to larger area requirements
Solution Approach 1:
Multiple bit lines are grouped together and connected to multiple memory cells through shared bit line groups. This merging reduces the total number of independent bit line connections needed, decreasing area occupancy and manufacturing cost while preserving the ability to individually address and operate on specific memory cells for non-volatile storage operations.
3Area of stationary object
If flash memory architecture is used, then small size and low cost are achieved, but single-bit programming is not allowed
Solution Approach 1:
The common source lines are selectively activated based on which memory cells need to be operated. By applying appropriate voltages to specific common source lines in combination with selected bit line groups and word lines, the system achieves local control over memory cell operations, enabling single-bit programming while maintaining the compact flash memory architecture.
4Area of stationary object
If EEPROM architecture with symmetric memory cell arrangement is used, then area is reduced, but current consumption during operation must be optimized
Solution Approach 1:
The patent implements dynamic voltage control of common source lines, where voltages are selectively applied or removed based on operational requirements. During write or erase operations, specific common source lines receive appropriate voltages; during idle periods, voltages are removed. This dynamic control optimizes current consumption while maintaining the reduced area benefits of symmetric memory cell arrangement.
Data Source
AI summary
A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.