Low-DC-Capacitance Inverter Layout for Reduced Parasitic Inductance
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Solution Overview
Problem
Existing power electronics converters in aerospace applications face limitations in efficiency and power-to-weight ratio due to high parasitic inductance in commutation cells, which leads to switching losses and heat generation, hindering performance improvements.
Innovation Solution
The design of power electronics converters with reduced parasitic inductance through surface-mounted power semiconductors, encapsulation in pre-packages, and direct electrical connections via vias, integrated on multi-layer carrier substrates, optimizing shape and connections to meet aerospace constraints while maintaining efficiency and power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power module topology with wire bonds is used, then availability and cost are improved, but parasitic inductance increases leading to reduced efficiency and power-to-weight ratio
Solution Approach 1:
The patent extracts and removes the wire bonds from the commutation cell, replacing them with direct soldered connections between power semiconductor components and the carrier substrate. This elimination of intermediate connection elements directly reduces parasitic inductance while maintaining component availability and reliability.
Solution Approach 2:
The patent transitions from planar wire bond connections to three-dimensional direct soldered connections, where power semiconductor components are mounted directly on the carrier substrate with vertical interconnections. This dimensional change enables shorter current paths and reduced loop areas, thereby reducing parasitic inductance.
2Ease of manufacture
If power module topology with wire bonds is used, then cost and availability are improved, but power-to-weight ratio deteriorates
Solution Approach 1:
The patent removes wire bonds from the commutation cell architecture, eliminating the need for these intermediate connection elements. This reduction in component count directly decreases the overall weight of the power electronics converter while maintaining manufacturing feasibility through direct soldering techniques.
Solution Approach 2:
By transitioning to direct mounted power semiconductor components with vertical connections on the carrier substrate, the patent reduces the spatial footprint and material requirements. This dimensional reorganization eliminates unnecessary connection elements and reduces overall converter weight.
3Ease of manufacture
If conventional electrical connections are used, then ease of manufacture is improved, but parasitic inductance increases reducing efficiency
Solution Approach 1:
The patent extracts and eliminates conventional wire bond connections from the commutation cell, replacing them with direct soldered connections. This removal of intermediate connection layers simplifies the manufacturing process while simultaneously reducing parasitic inductance and switching losses.
Solution Approach 2:
The patent transitions from planar wire bond connections to three-dimensional direct soldered connections, creating vertical current paths that are shorter and have lower inductance. This dimensional change maintains manufacturing ease through automated soldering while dramatically reducing parasitic effects.
4Power
If DC link capacitor size is reduced, then power density is improved, but voltage ripple increases affecting performance
Solution Approach 1:
The patent changes the electrical parameters of the DC link capacitor, specifically reducing its capacitance value while compensating for the increased voltage ripple through optimized power semiconductor switching characteristics and improved commutation cell design with reduced parasitic inductance.
Solution Approach 2:
The patent converts the potentially harmful effect of reduced capacitance (increased voltage ripple) into a benefit by using the smaller capacitor to reduce overall converter volume and weight. The reduced parasitic inductance in the commutation cell compensates for the voltage ripple, allowing the system to achieve higher power density without performance degradation.
Data Source
AI summary
A power electronics converter may include: a converter commutation cell having a power circuit and a gate driver circuit, the power circuit including at least one power semiconductor switching element and at least one capacitor, wherein each power semiconductor switching element is embedded in a solid insulating material, wherein each power semiconductor switching element has at least three terminals including a gate terminal, wherein the gate driver circuit is electrically connected to and configured to provide switching signals to the gate terminal of each power semiconductor switching element, wherein a peak rated power output of the power electronics converter is greater than 25 KW, and wherein a total rated capacitance of the power circuit of the converter commutation cell divided by the peak rated power output of the power electronics converter is less than or equal to 5 nF/W.