Low Dielectric Pattern Burial for Transistor Interference Suppression
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Solution Overview
Problem
As integrated circuit semiconductor devices become more integrated, the decreasing size of transistors leads to increased interference effects, making it difficult to fabricate reliable devices due to electrical or physical interference between transistors.
Innovation Solution
A fabrication method involving the formation of low dielectric patterns with a lower dielectric constant than the substrate, buried by a flow layer and an epitaxial layer, which helps in suppressing the interference effect between transistors by creating a barrier and improving gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are made smaller to increase integration, then device integration is improved, but interference effect between transistors increases
Solution Approach 1:
A flow layer is introduced as an intermediary structure between adjacent transistors. This flow layer has a higher dielectric constant than the surrounding low dielectric material, creating a barrier that suppresses the interference effect between closely spaced transistors while allowing them to remain small for high integration.
Solution Approach 2:
The dielectric constant is varied locally in the substrate. Low dielectric material is used in regions between transistor channels to reduce overall capacitance, while high dielectric material is strategically placed in the flow layer beneath specific transistor regions to suppress interference effects where needed, creating a non-uniform dielectric structure optimized for different functional requirements.
2Object-affected harmful factors
If low dielectric material is used to reduce interference, then electrical isolation is improved, but depletion region control becomes difficult
Solution Approach 1:
The dielectric structure is made non-uniform with low dielectric material in channel regions for electrical isolation and high dielectric material in flow layers for depletion region control. This local variation in dielectric properties allows simultaneous optimization of both electrical isolation and depletion region suppression.
Solution Approach 2:
The substrate structure combines multiple dielectric materials with different dielectric constants. The low dielectric material provides electrical isolation between adjacent devices, while the high dielectric material in the flow layer provides the necessary electric field control for depletion region suppression, creating a composite dielectric system that addresses both requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the interference effect between transistors, enhancing the reliability of integrated circuit semiconductor devices by improving the suppression of depletion regions and electrical isolation.
Implementation Method 1
forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate
Implementation Method 2
forming an epitaxial layer on the flow layer
Data Source
AI summary
A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.