Low-Dimensional FinFET Gate Length Control via Self-Assembled Spacers
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient manufacturing of low-dimensional FinFETs due to limitations in controlling the length of gate structures and contact resistance in existing semiconductor fabrication processes.
Innovation Solution
The formation of low-dimensional FinFETs involves creating a low-dimensional layer for source/drain and channel regions, with self-assembled spacers controlling the gate structure length and source/drain contact formation to reduce resistance, using materials like carbon nanotubes or transition metal dichalcogenides, and patterning techniques to achieve precise dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to form gate structures, then manufacturing simplicity is maintained, but gate structure length control precision deteriorates
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacer width automatically defines the gate length. The spacer is formed conformally on the source/drain regions, and subsequent etching uses the spacer as a self-aligned mask, eliminating the need for separate lithography alignment steps. This self-service mechanism achieves precise gate length control while simplifying the overall fabrication process.
Solution Approach 2:
The patent performs preliminary formation of source/drain contacts with controlled dimensions before forming the gate structure. The source/drain contacts are patterned and etched to precise widths that serve as templates for subsequent spacer formation. This preliminary action establishes the geometric constraints that will automatically define the gate length in later self-aligned steps.
2Productivity
If minimum feature size is reduced to improve integration density, then component integration increases, but manufacturing precision challenges worsen
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows the channel length to be defined by the horizontal footprint while the channel height is provided by the vertical fin dimension, enabling better electrostatic control and improved manufacturing precision at scaled dimensions.
Solution Approach 2:
The self-aligned spacer formation process inherently controls feature dimensions through the spacer thickness rather than lithographic patterning. The spacer width, controlled by conformal deposition thickness, automatically defines the gate length and source/drain contact spacing, providing manufacturing precision that is less sensitive to lithography resolution limits.
3Productivity
If source/drain contact dimensions are reduced to improve integration, then integration density increases, but contact resistance increases
Solution Approach 1:
The patent implements a multi-layer contact structure where lower contacts are formed first, then upper contacts are formed over them, creating a nested vertical contact architecture. This nested structure increases the total contact area and volume without increasing the lateral footprint, thereby reducing contact resistance while maintaining high integration density.
Solution Approach 2:
The patent uses composite contact structures combining different materials with complementary properties. The contact structure includes multiple material layers that provide both low resistance pathways and good adhesion to semiconductor regions, achieving reduced contact resistance through material composition rather than increased dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved electrostatic control, reduced contact resistance, and flexible manufacturing of low-dimensional FinFETs with controlled channel and gate lengths, enhancing performance and integration density.
Implementation Method 1
The length of the gate structure may be controlled in a self-aligned manner by forming temporary self-assembled spacers on the source/drain contacts
Implementation Method 2
a low-dimensional layer used to form source/drain regions and a channel region
Data Source
AI summary
In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.