Low-Dimensional Material Transistor FinFET Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in forming transistors with high carrier mobility and small energy bandgap values, particularly due to the limitations of traditional channel materials in integrated circuit fabrication.
Innovation Solution
The formation of transistors using low-dimensional materials such as carbon nanotube networks, aligned carbon nanotubes, and Transition Metal Dichalcogenides (TMDs) as channel materials, which are stacked and patterned into a protruding fin structure to create FinFET or Gate-All-Around transistors, allowing for high carrier mobility and reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional channel materials are used in transistor fabrication, then manufacturing processes are simple and compatible with existing technology, but carrier mobility is limited and energy bandgap values are not sufficiently small
Solution Approach 1:
The patent changes the material parameters by transitioning from traditional bulk semiconductor materials to low-dimensional materials (2D materials like TMDs and carbon nanotubes). This material parameter change enables high carrier mobility and small energy bandgap while maintaining compatibility with existing fabrication processes through established deposition and patterning techniques
Solution Approach 2:
The patent employs composite material structures by stacking multiple low-dimensional material layers with insulating layers to form FinFET or Gate-All-Around transistor structures. This composite approach combines the high carrier mobility of low-dimensional materials with the structural benefits of vertical stacking to achieve both performance improvement and manufacturing compatibility
2Reliability
If traditional planar transistor structures are used, then manufacturing is straightforward, but short-channel effects are significant and limit device performance
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) FinFET and Gate-All-Around structures by stacking low-dimensional material layers. This dimensional change provides better gate control over the channel, significantly reducing short-channel effects while maintaining manufacturing feasibility through adapted fabrication processes
3Reliability
If low-dimensional materials are stacked and patterned into protruding fin structures, then high carrier mobility and reduced short-channel effects are achieved, but fabrication process complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct stacked layers of low-dimensional materials and insulators that form protruding fins. This segmentation allows each layer to be formed and patterned separately using existing fabrication techniques, making the complex 3D structure manufacturable through sequential processing steps
Data Source
AI summary
A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.