Low-Elasticity Resin Substrate for IC Mounting
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Solution Overview
Problem
Conventional IC chip mounting technologies using solder bumps result in high electrical resistance, voltage drops, and complex manufacturing processes, leading to potential IC chip malfunctions and increased operational complexity.
Innovation Solution
A substrate with a low-thermal-expansion ceramic or silicon substrate and a low-elasticity resin layer, connected through-hole conductors that eliminate the need for soldering, reducing electrical resistance and simplifying the manufacturing process by allowing smooth power supply to the IC chip and absorbing thermal expansion stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used to connect the interposer and package substrate, then the connection is established, but the electrical resistance is high causing voltage drop
Solution Approach 1:
The patent replaces the mechanical solder bump connection system with a direct conductive connection system using conductive adhesive or metal plates. This substitution eliminates the high electrical resistance inherent in solder bumps while maintaining mechanical connection, thereby reducing voltage drop and improving power supply stability to the IC chip.
Solution Approach 2:
The patent changes the connection method from solder bumps (high resistance) to conductive adhesive or metal plates (low resistance). This parameter change in electrical resistance directly addresses the voltage drop issue by providing a low-resistance path for electrical current, ensuring stable voltage supply even during high power consumption moments.
2Reliability
If solder bumps are used for connection, then electrical connection is achieved, but the manufacturing process becomes complex
Solution Approach 1:
The patent extracts the soldering process from the manufacturing sequence by replacing it with simpler attachment methods such as conductive adhesive bonding or mechanical mounting. This removal of the complex reflow soldering step, along with eliminated underfill filling and alignment operations, significantly simplifies the manufacturing process while maintaining connection stability.
Solution Approach 2:
The patent employs conductive adhesive or simple mechanical mounting structures that are easier and faster to apply than solder bumps. These alternative connection methods require no specialized soldering equipment or complex process control, reducing manufacturing complexity and enabling simpler, more reliable production.
3Reliability
If an interposer is mounted on package substrate, then connection is established, but alignment and soldering operations are complex
Solution Approach 1:
The patent replaces the complex mechanical soldering and alignment system with a simplified attachment system using conductive adhesive or direct mounting. This substitution eliminates the need for precise alignment and reflow soldering operations, making the interposer mounting process much simpler while maintaining reliable electrical and mechanical connections.
4Power
If solder bumps are used, then connection is made, but voltage drop occurs during high power consumption
Solution Approach 1:
The patent fundamentally changes the electrical resistance parameter of the connection path by replacing solder bumps with conductive adhesive or metal plate connections. This parameter change reduces electrical resistance from high (solder) to low (conductive adhesive/metal), enabling stable power supply during high current moments and preventing voltage drop that would cause IC chip malfunction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable voltage supply to IC chips during high power consumption, prevents malfunctions, simplifies manufacturing by eliminating complex soldering operations, and enhances yield and heat dissipation properties while reducing internal wire breakage risks.
Implementation Method 1
the stress generated by the difference in thermal expansion coefficient between the printed substrate and the low-thermal-expansion substrate may be absorbed by the low-elasticity resin layer
Implementation Method 2
The through-hole conductors electrically connect the first conductor layer and the second conductor circuits provided on the low-thermal-expansion substrate
Data Source
AI summary
A substrate for mounting an IC chip including a printed substrate including a first build-up layer. The first build-up layer including (i) a first conductor layer having first conductor circuits and (ii) a resin insulating layer. The first conductor circuits and the resin insulating layer alternating along a length of the first build-up layer. A low-elasticity resin layer formed on the first build-up layer. A low-thermal-expansion substrate formed of ceramics or silicon, and provided on the low-elasticity resin layer. Through-hole conductors provided through the low-thermal-expansion substrate and the low-elasticity resin layer; and second conductor circuits formed on the low-thermal-expansion substrate. The through-hole conductors electrically connect the first conductor layer and the second conductor circuits provided on the low-thermal-expansion substrate.