Low Energy Accelerator Processor Architecture for Vector Operations
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Solution Overview
Problem
Existing microcontroller units (MCUs) face challenges in reducing power consumption while maintaining computational performance, particularly in vector operations, due to the increased silicon area and transistors required by added digital signal processors (DSPs) and dedicated hardware accelerators, which are inflexible and inefficient.
Innovation Solution
A low energy accelerator processor architecture with a short parallel instruction word and optimized instruction set is introduced, featuring a central processor unit, load store unit, multiply unit, and butterfly/adder ALU, optimized for vector computations, reducing gate count and silicon area, and enabling efficient execution of vector operations with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a digital signal processor (DSP) is added to increase computational performance for vector operations, then computation speed is improved, but active device power consumption increases proportionally with the number of transistors
Solution Approach 1:
The processor is segmented into distinct execution units (load/store unit, multiply unit, adder unit, butterfly unit) that can be selectively activated. Each unit handles specific vector operations independently, allowing the system to activate only the necessary units for each computational task, thereby reducing overall power consumption while maintaining high computation speed for vector operations.
Solution Approach 2:
The processor employs dynamic activation of execution units based on the specific computational requirements. The control logic selectively enables or disables execution units depending on whether vector operations are being performed, allowing the system to adapt its power consumption to the actual computational workload rather than operating at full power continuously.
2Productivity
If dedicated hardware accelerators are added to perform specific vector computations, then computational performance is improved, but device complexity and silicon area increase
Solution Approach 1:
The processor implements a universal vector processing architecture where a single set of execution units (load/store, multiply, adder, butterfly units) can perform multiple vector operations including FFT, FIR filtering, IIR filtering, and other signal processing functions. This multi-functional design eliminates the need for separate dedicated hardware accelerators for each vector operation, reducing device complexity while maintaining high computational performance across various vector computation types.
3Productivity
If vector processing capabilities are added to general purpose microprocessors, then computational performance for signal processing is improved, but the number of transistors and silicon area increase
Solution Approach 1:
The processor merges general-purpose microprocessor functionality with specialized vector processing capabilities into a unified architecture. The execution units are designed to handle both general-purpose computations and vector operations using the same transistor resources, particularly through the use of a unified data path and register file that serves both scalar and vector operations, thereby reducing the total number of transistors required compared to having separate dedicated vector processing units.
Data Source
AI summary
Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.