Low to High Speed Transition Circuit for Memory Interfaces
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Solution Overview
Problem
Conventional high-speed memory interfaces experience significant performance degradation due to lengthy bus idle times when transitioning from low-speed to high-speed mode, as the analog timing circuitry requires time to power up and stabilize, leading to delays that can result in missed real-time constraints and performance losses.
Innovation Solution
A low to high speed transition circuit that allows the memory device and controller to operate in low-power mode during initialization of analog timing circuitry, using a forward clock to lock the PLL concurrently, reducing idle time by enabling phase detection and correction only when necessary, and employing a multiplexer to switch between low-speed digital and high-speed analog timing logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the analog timing circuitry is powered up during transition to high-speed mode, then the high-speed operation can be achieved, but the bus idle time increases significantly due to power-up and stabilization requirements
Solution Approach 1:
The patent applies preliminary action by initiating the PLL frequency transition before the mode switch is complete. Specifically, the PLL is instructed to transition to the high-speed frequency 200-400 clock cycles before the actual mode transition, allowing the timing circuitry to be pre-configured and ready, thereby minimizing the bus idle time when high-speed operation begins.
2Loss of time
If the PLL frequency is transitioned early to prepare for high-speed mode, then the transition time is reduced, but the timing circuitry cannot change frequency during high-speed operation
Solution Approach 1:
The patent implements dynamics by creating a time-dependent frequency transition strategy. The system dynamically adjusts the PLL frequency based on the operational phase: during low-speed mode, the PLL operates at low frequency; during the transition period, it switches to high frequency; and during high-speed mode, it maintains high frequency. This dynamic frequency adjustment optimizes both transition time and operational adaptability.
Data Source
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AI summary
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.