Low-Inductance Bus Assembly for High-Speed Power Converter Switching
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Solution Overview
Problem
Conventional power converter apparatus using silicon-based semiconductor switching devices are limited to operating voltages less than 10 kV and switching frequencies less than 100 kHz, while wide bandgap semiconductor switching devices face issues with significant voltage and current transients due to parasitic inductance and capacitance from interconnecting bus bars, limiting their full utilization.
Innovation Solution
A power converter apparatus with a bus assembly comprising core bus plates and extension plates arranged in specific configurations to reduce parasitic inductance, featuring rounded joints and parallel bus structures to enhance current distribution and minimize arcing, utilizing wide bandgap semiconductor switching devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wide bandgap semiconductor switching devices are used to operate at higher frequencies and voltages, then switching speed and operating voltage are improved, but parasitic inductance and capacitance from interconnecting bus bars cause significant voltage and current transients
Solution Approach 1:
The bus bar is segmented into multiple parallel conductors (first bus bar, second bus bar, third bus bar, fourth bus bar) arranged in a compact configuration. This segmentation reduces the loop area and distributes the current path, thereby reducing parasitic inductance and the resulting voltage and current transients during high-speed switching operations.
Solution Approach 2:
Multiple bus bars are merged into a single integrated bus assembly with parallel conductors positioned close together. This merging creates a compact structure that minimizes the overall loop area and reduces parasitic inductance while maintaining the ability to handle high currents at high switching frequencies.
2Reliability
If conventional silicon-based semiconductor switching devices are used, then operating voltage and switching frequency are limited to less than 10 kV and 100 kHz, but parasitic inductance and capacitance issues are reduced
Solution Approach 1:
The bus bar geometry is optimized by changing parameters such as conductor width, spacing between parallel conductors, and overall arrangement to minimize parasitic inductance. This allows the system to support higher switching frequencies and voltages required by wide bandgap devices while maintaining operational stability.
Data Source
AI summary
An apparatus, such as a power converter, includes first, second and third core bus plates arranged in parallel. The apparatus also includes a first bus extension plate joined to the first core bus plate and extending therefrom at a first angle and a second bus extension plate joined to the second core bus plate and extending therefrom at a second angle. The apparatus further includes a third bus extension plated joined with the third core bus plate and disposed parallel to the first bus extension plate and a fourth bus extension plate joined with the third core bus plate and disposed parallel to the second bus extension plate.