Low-Inductance DC Power Bus for SiC and GaN Applications
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Solution Overview
Problem
Current DC power bus designs in electric vehicles and photovoltaic power converters are limited by high parasitic inductance, which increases ripple voltage and can damage transistors, especially at higher switching frequencies and temperatures, and are not optimized for wide bandgap materials like SiC and GaN.
Innovation Solution
A new DC bus design using a printed circuit board with multiple ceramic capacitors in parallel and large metal conductors to reduce inductance, combined with improved thermal management, allowing operation at higher frequencies and temperatures, and eliminating the need for separate snubbing capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capacitors are used to smooth current spikes in typical DC power buses, then the shunt impedance is reduced and current ripple is decreased, but the parasitic inductance increases which actually increases ripple voltage at high switching frequencies
Solution Approach 1:
The patent divides the single large capacitor into multiple smaller capacitors (e.g., six 680 µF capacitors instead of one large capacitor). This segmentation reduces the parasitic inductance of the capacitor bank while maintaining the total capacitance value, thereby reducing ripple voltage at high switching frequencies while preserving current smoothing capability
Solution Approach 2:
The patent implements a nested capacitor configuration where capacitors are arranged in a compact, interlocking pattern with overlapping connections. This nesting minimizes the loop area and parasitic inductance by creating tightly coupled current paths, effectively reducing the harmful inductive effects while maintaining the required capacitance for current smoothing
2Ease of manufacture
If conventional film capacitors are used in DC power buses, then the design is simple and cost-effective, but the heat conduction is poor and reliability deteriorates at temperatures substantially greater than 100°C
Solution Approach 1:
The patent employs a hybrid capacitor design combining film capacitors and ceramic capacitors. The film capacitors provide bulk capacitance and cost-effectiveness, while the ceramic capacitors (with superior thermal conductivity and high-temperature stability) are strategically placed near heat-generating components. This composite approach maintains design simplicity while dramatically improving high-temperature reliability through enhanced heat dissipation pathways
3Reliability
If DC power bus designs are optimized for silicon IGBTs with switching frequencies around 10 kHz, then the system works reliably at lower frequencies, but the design is not suitable for wide bandgap materials like SiC and GaN that operate at 100 kHz and above
Solution Approach 1:
The patent fundamentally changes the electrical parameters of the DC power bus by reducing parasitic inductance through segmented and nested capacitor configurations. This parameter change shifts the resonant frequency of the bus upward, making it compatible with high-frequency wide bandgap devices (SiC, GaN) operating at 100 kHz and above, while maintaining stable operation at lower frequencies. The design becomes adaptable across a broad frequency range rather than being optimized for a single frequency regime
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces parasitic inductance, enabling higher-frequency operation, improved thermal management, and increased power density, making it suitable for wide bandgap devices like SiC and GaN transistors, while reducing the size and cost of the DC link capacitor.
Implementation Method 1
It does this by using parallel capacitors to provide a low shunt impedance to the high-frequency current components in order to smooth out current spikes created by the switching operations
Implementation Method 2
A new DC bus design using a printed circuit board with multiple ceramic capacitors in parallel and large metal conductors to reduce inductance
Data Source
AI summary
A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.