Low-Inductance Micro-Copper Traces for On-Package Power Distribution
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Solution Overview
Problem
Current semiconductor device packaging faces challenges in achieving high-speed and small volume interconnects between dice while effectively delivering power to capacitors, particularly in multi-chip packages, where existing solutions often result in high inductance paths that hinder efficient power delivery and capacitance distribution.
Innovation Solution
The implementation of micro-Copper (μCu) traces with specific thicknesses and dielectric layers in semiconductor packages creates low-inductance alternating-current paths that allow for efficient power delivery to die-side capacitors, preserving useful ball array populations and optimizing capacitance distribution, and can be made from materials like silver to reduce inductance and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional power distribution paths are used in multi-chip packages, then device miniaturization and integration are achieved, but loop inductance and AC impedance increase, hindering efficient power delivery
Solution Approach 1:
The patent transitions from planar two-dimensional power distribution traces to three-dimensional vertical power delivery paths using through-silicon vias (TSVs) and stacked capacitor configurations. This dimensional change enables shorter current loops and reduced inductance by exploiting the vertical dimension for direct power delivery from package substrate through die to capacitors, resolving the contradiction between miniaturization and power delivery efficiency.
Solution Approach 2:
The patent changes the physical parameters of power distribution by using thinner, lower-inductance trace geometries and optimizing via dimensions. By adjusting trace width, thickness, and via hole sizes, the design achieves lower loop inductance and AC impedance while maintaining compact package dimensions, thereby improving power delivery efficiency without increasing package volume.
2Reliability
If more die-side capacitors are added to reduce impedance, then capacitance distribution is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple capacitor functions into fewer strategically positioned die-side capacitors by optimizing their connection through low-inductance TSV paths. Instead of distributing many capacitors across the die, the design uses fewer capacitors with enhanced vertical interconnects that provide equivalent or superior capacitance distribution, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The patent introduces low-inductance TSV structures as intermediary elements that efficiently couple die-side capacitors to power delivery networks. These TSV intermediaries enable fewer capacitors to achieve better capacitance distribution by providing optimized electrical pathways that reduce inductance and improve the effectiveness of each capacitor in the array.
3Reliability
If thicker traces are used to reduce inductance, then power delivery efficiency is improved, but manufacturing precision requirements and device complexity increase
Solution Approach 1:
The patent optimizes trace thickness parameters to achieve the optimal balance between inductance reduction and manufacturing feasibility. By using moderate trace thicknesses combined with vertical TSV interconnects, the design achieves low inductance without requiring extreme precision in trace thickness control, thereby improving power delivery efficiency while maintaining reasonable manufacturing precision requirements.
Data Source
AI summary
A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.