Low Inductance Power Switch Circuit Board Layout
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Solution Overview
Problem
Circuit board layouts for power switched circuits often limit performance due to high parasitic inductance, which negatively impacts switching speed and Electromagnetic Interference (EMI) generation, despite advancements in power FET technologies like silicon metal oxide semiconductor FETs and gallium nitride transistors.
Innovation Solution
A multilayer circuit board design with a first layer featuring a transistor switch, load, and bus capacitor, where the capacitor is centrally mounted between the switch and load, and separate conductors for switch load and gate drive currents, along with a second layer carrying switch load current in an opposite direction, reducing common source inductance and total parasitic inductance through parallel wide conductors and ground planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional circuit board layouts are used for power switched circuits, then component placement is simplified, but parasitic inductance increases which degrades switching performance
Solution Approach 1:
The patent utilizes a multilayer circuit board structure where power and ground traces are placed on different layers. This vertical separation in the Z-dimension allows current loops to be minimized while maintaining planar component placement. The power trace on one layer and return path on another layer creates tightly coupled loops that reduce parasitic inductance without complicating component layout.
Solution Approach 2:
The patent implements different trace configurations in different regions of the circuit board. Near the power switch, the layout uses tight coupling between power and ground traces with minimal loop area. In other regions, standard routing practices can be used. This localized optimization reduces parasitic inductance where it matters most while maintaining overall design simplicity.
2Speed
If fast switching speeds are achieved through advanced FET technologies, then power conversion efficiency improves, but parasitic inductance becomes a limiting factor that increases EMI
Solution Approach 1:
The patent pre-empts EMI issues by designing the circuit board layout to minimize parasitic inductance before the switching transients occur. The power and ground traces are routed to create the smallest possible loop area adjacent to the power switch, and decoupling capacitors are positioned with minimal inductance paths to the switch terminals. This preliminary optimization prevents EMI generation at its source rather than attempting to mitigate it afterward.
Solution Approach 2:
The patent uses decoupling capacitors as intermediary elements between the power source and the power switch. These capacitors are strategically placed with low-inductance connections to provide local energy storage during switching transitions, reducing the di/dt through the parasitic inductance and thereby minimizing EMI. The capacitors act as buffers that mediate the high-frequency current demands of fast switching.
3Speed
If common source inductance is reduced through separate conductors for load and gate currents, then switching speed increases, but conductor routing complexity increases
Solution Approach 1:
The patent segments the current paths by providing separate dedicated conductors for power, ground, and gate signals. The power trace and ground trace are kept separate with minimal parallel coupling except where necessary for decoupling capacitor connections. The gate signal trace is routed separately from power traces. This segmentation eliminates common source inductance while the systematic routing approach keeps the increased complexity manageable through clear design rules.
Data Source
AI summary
A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.