Low-Jitter Divide-by-2 Clock Circuit With Narrow Pulse Control
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Solution Overview
Problem
Traditional divide-by-2 frequency division clock circuits in A/D converters suffer from high jitter due to noise contribution from logic gates and power supply sensitivity, limiting their ability to meet the requirements of high-speed and high-precision applications.
Innovation Solution
A low-jitter frequency division clock circuit design that reduces the number of logic gates and incorporates a positive feedback loop to minimize rising and falling edge times, using a clock control signal generation circuit, low-level and high-level narrow pulse width clock control signal generation circuits, and a frequency division clock generation circuit with NMOS and PMOS transistors to generate a frequency division clock signal with reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a traditional D flip-flop frequency division circuit is used, then the structure is simple and easy to implement, but the jitter is large due to noise from multiple logic gates and power supply sensitivity
Solution Approach 1:
The patent extracts and eliminates the problematic elements from the traditional D flip-flop circuit. Specifically, it removes the master clock input from the D flip-flop's clock input to prevent noise propagation through multiple logic gates. Instead, the master clock is connected directly to the output buffer, creating a clean reference path that bypasses the noisy logic gate chain.
Solution Approach 2:
The patent introduces an intermediary mechanism - a specialized frequency division circuit structure that acts as a mediator between the master clock and the output. This circuit uses controlled signal paths and buffering to intermediate the clock signal transmission, reducing direct noise coupling and power supply sensitivity while maintaining the frequency division function.
2Power
If multiple buffers are inserted to increase output drive capability, then the load driving ability improves, but the jitter increases due to additional logic stages
Solution Approach 1:
The patent segments the output stage into dedicated buffer components that are separately optimized for drive capability. Instead of using general-purpose logic gates as buffers, it employs specific buffer circuits that provide high drive strength without adding significant propagation delay or noise. This segmentation allows the output stage to be optimized independently for both power and reliability.
3Productivity
If the clock signal passes through multiple logic gates, then the frequency division function is achieved, but the noise from each logic gate accumulates and increases output noise
Solution Approach 1:
The patent extracts the harmful noise generation path by removing the master clock signal from the D flip-flop's clock input. This eliminates the propagation of clock edges through multiple logic gates, which is the primary source of noise accumulation. The frequency division function is maintained through alternative signal paths that do not involve cascaded logic gate operations on the master clock.
Data Source
AI summary
The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.