Low Jitter Clock Generator Using Amplitude Control and Filtering
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Solution Overview
Problem
Existing clock generator systems for high data communication rates, such as SONET and Gigabit-Ethernet, face challenges in achieving low jitter due to noise and harmonic amplification in frequency multiplication processes, which are costly and provide poor performance with high frequency selectivity and noise sensitivity.
Innovation Solution
A circuit comprising an oscillator, two frequency multipliers, filters, and feedback circuits to control the amplitude of the oscillation signal, minimizing undesired frequency components and maintaining a constant output amplitude despite gain variations, using zero-degree RF double-balanced mixers and bandpass filters for reduced noise and harmonic content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency multiplication is employed to generate clock frequencies above 160 MHz, then the clock frequency is improved, but phase noise and distortion are added resulting in increased jitter
Solution Approach 1:
The patent applies preliminary action by controlling the amplitude of the oscillation signal before it enters the frequency multiplier. The amplitude control circuit adjusts the signal amplitude to an optimal level prior to multiplication, which minimizes the generation of phase noise and distortion during the frequency multiplication process, thereby reducing jitter in the final clock signal.
Solution Approach 2:
The patent implements feedback through an amplitude control circuit that monitors the oscillation signal and adjusts its amplitude accordingly. This feedback mechanism ensures the signal maintains an optimal amplitude level throughout the frequency multiplication process, preventing excessive phase noise and distortion that would otherwise increase jitter.
2Object-affected harmful factors
If summing resulting frequencies from mixers is used to reduce noise and harmonics, then noise and harmonics are reduced, but the circuit complexity and cost increase
Solution Approach 1:
The patent applies the taking out principle by extracting and removing unwanted frequency components (noise and harmonics) using a bandpass filter. Instead of using complex summing circuits to reduce noise, the invention selectively extracts the desired frequency component while rejecting unwanted ones, achieving noise reduction with simpler circuitry.
Solution Approach 2:
The patent introduces a bandpass filter as an intermediary component between the frequency multiplier and the output. This filter acts as a mediator that selectively passes the desired frequency while blocking noise and harmonics, achieving noise reduction without requiring complex summing circuits.
3Object-affected harmful factors
If 90-degree quadrature mixers are used to reduce noise and harmonics, then noise and harmonics are reduced, but the number of active elements increases creating more noise and distortion
Solution Approach 1:
The patent replaces complex 90-degree quadrature mixers with a simpler frequency multiplier design that uses fewer active elements. While the simpler design may have limitations, it achieves acceptable noise and harmonic reduction through the bandpass filter without introducing the additional noise and distortion that would result from using more complex mixer circuits.
4Object-affected harmful factors
If 90-degree quadrature mixers are used, then noise and harmonics are reduced, but the circuit becomes highly frequency dependent requiring redesign for different frequencies
Solution Approach 1:
The patent achieves universality by designing a frequency multiplier circuit that can operate at different frequencies without requiring redesign. The use of a bandpass filter instead of frequency-specific 90-degree quadrature mixers allows the circuit to maintain its noise and harmonic reduction capabilities across a broader frequency range, making it adaptable to different clock frequency requirements.
Data Source
AI summary
A circuit for generating an output oscillation signal with low jitter includes an oscillator to generate an oscillation signal at an initial frequency based upon a control input to vary an amplitude of the oscillation signal. A first frequency multiplier multiplies the oscillation signal to result in a first signal with first frequency and first undesired frequency components. A filter minimizes the first undesired frequency components of the first signal. A second frequency multiplier multiplies the first signal to result in the output oscillation signal with second frequency and second undesired frequency components. A second feedback circuit compares a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value. A first feedback circuit varies the control input based upon a comparison between the reference value and the amplitude of the oscillation signal to minimize the second undesired frequency components.