Tunable Low-k Inner Air Spacers for CMOS RC Delay Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the RC delay of CMOS transistors due to increasing complexity in manufacturing processes as devices scale down, necessitating the use of low-k dielectric materials to lower capacitance between gate structures and epitaxial source/drain regions.
Innovation Solution
The implementation of tunable low-k inner air spacers sealed by dielectric spacer layers between the gate structure and epitaxial source/drain regions in FETs, which can be formed using a two-step or one-step low-k dielectric spacer layer deposition method, reduces the dielectric constant and capacitance, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to lower capacitance between gate structures and epitaxial source/drain regions, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The spacer structure is divided into multiple segments: an inner air spacer and outer dielectric spacers. This segmentation allows the air spacer to provide low-k benefits while the outer dielectric spacers protect the structure and enable standard manufacturing processes, thus improving device performance without proportionally increasing manufacturing complexity
Solution Approach 2:
The inner air spacer is nested within the outer dielectric spacers, creating a hierarchical structure. This nesting allows the air spacer to be protected during manufacturing while still providing its low-k dielectric benefits, resolving the contradiction between performance improvement and manufacturing complexity
2Reliability
If air spacers are used to reduce dielectric constant, then capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The air spacer is formed preliminarily before the outer dielectric spacers are deposited. This preliminary action defines the air spacer geometry early in the process, and the subsequent outer spacers are formed conformally around it, reducing the precision requirements for the overall structure while maintaining the low-k benefits
Solution Approach 2:
The outer dielectric spacers act as an intermediary layer that protects the inner air spacer during subsequent manufacturing steps. This intermediary structure reduces the precision requirements for handling the air spacer directly, as the robust outer spacers provide mechanical support and protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of FETs by 2% to 15% by reducing capacitance and RC delay, leading to faster transistor speeds and improved semiconductor device performance.
Implementation Method 1
low-k dielectric spacer layers deposited at a same deposition rate within. The inner air spacer reduces the dielectric constant and capacitance between the gate structure and the epitaxial source/drain regions
Data Source
AI summary
The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.