Low-k Bitline Spacer Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor technology advances to nanoscale, there is a need for improved isolation structures within memory arrays to effectively isolate conductive elements, which existing technologies have not adequately addressed.
Innovation Solution
A manufacturing method involving the formation of a SiCO spacer with a carbon concentration of 10% to 20% and a dielectric constant of 2 to 3, which includes a sacrificial layer etching process using oxygen plasma to create trenches and form contacts, while also incorporating porogens to create voids in the spacer for reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional isolation structures are used in nanoscale semiconductor devices, then manufacturing is simpler, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The spacer is formed as a porous low-k dielectric material with a dielectric constant of 2 to 3, significantly lower than conventional materials. This porous structure reduces parasitic capacitance between the bitline and conductive features, thereby reducing power consumption while maintaining isolation functionality
Solution Approach 2:
The invention uses a composite structure combining the low-k porous spacer material with a sacrificial layer (such as carbon-containing material or silicon nitride). This composite approach enables selective etching processes that create precise trenches while maintaining the integrity of the low-k spacer, achieving both low parasitic capacitance and manufacturability
2Loss of energy
If a low-k porous spacer is formed to reduce parasitic capacitance, then power consumption decreases, but the manufacturing process becomes more complex
Solution Approach 1:
The sacrificial layer is formed over the low-k porous spacer material before trench etching. This preliminary action protects the delicate porous structure during subsequent processing steps and enables selective removal of specific regions to form trenches, simplifying the overall manufacturing process despite the complexity of the low-k material
Solution Approach 2:
The sacrificial layer acts as an intermediary material that facilitates the formation of trenches in the low-k spacer. By using this intermediate layer with different etching characteristics, the process enables precise trench formation without directly etching the porous low-k material, thereby simplifying manufacturing
3Reliability
If trenches are formed in the spacer to create contacts, then electrical connection is achieved, but the spacer structure is compromised
Solution Approach 1:
The spacer structure is segmented into different regions: intact low-k porous material regions that maintain isolation and reduce parasitic capacitance, and trench regions that provide electrical connection paths. This segmentation allows the spacer to simultaneously fulfill both isolation and connection functions
Solution Approach 2:
The spacer exhibits local quality variations with low-k porous material in isolation regions and etched trenches in connection regions. This local differentiation enables the spacer to provide low parasitic capacitance where needed while allowing electrical connections where required, maintaining both reliability and functional integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of low-k spacers that reduce active power consumption and improve performance by minimizing parasitic capacitances, while simplifying the manufacturing process and reducing costs.
Implementation Method 1
removing the remaining portion of the sacrificial layer is performed by an etching process that has an etching selectivity between the first spacer and the sacrificial layer... removing the remaining portion of the sacrificial layer comprises using an oxygen plasma to etch the remaining portion of the sacrificial layer
Implementation Method 2
the spacer has a dielectric contact in a range of about 2 to about 3... the first spacer is made of SiCO... the spacer has voids therein... a dielectric constant of the spacer is in a range from 2 to 3
Implementation Method 3
heating the spacer to remove the porogens in the dielectric material to form voids in the dielectric material... heating the first spacer is performed at a temperature in a range from 350° C. to 400° C
Data Source
AI summary
A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.