Low-k Isolated Bump Structure for Reliable Fine-Pitch Interconnects
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Solution Overview
Problem
The reduction in size of semiconductor device bumps increases the likelihood of failure due to their smaller size, necessitating a more reliable isolation structure for bump solder joints in three-dimensional integrated circuits and micro electro mechanical systems (MEMS).
Innovation Solution
A novel bump structure is developed with an isolation structure made of low-k dielectric material, functioning as an etch stop layer and improving mechanical strength while maintaining low parasitic capacitance, which includes a trench filled with insulating material and conductive layers formed using techniques like PVD and CVD, ensuring reliable electrical isolation and increased process friendliness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If bump size is reduced to enable device miniaturization, then device size decreases, but reliability of bump solder joints deteriorates
Solution Approach 1:
The bump structure is segmented into multiple functional layers: a bump electrode, an isolation structure with insulating material, and conductive layers. This segmentation allows the smaller bump to have enhanced reliability through the distributed isolation and support structures, preventing solder joint failure while maintaining miniaturization.
Solution Approach 2:
An isolation structure consisting of insulating material (such as low-k dielectric material) is introduced as an intermediary between adjacent bump electrodes. This isolation structure prevents electrical leakage and enhances the reliability of individual bump solder joints, allowing smaller bumps to be used without compromising reliability.
2Reliability
If isolation structure is added to improve reliability, then reliability increases, but device complexity increases
Solution Approach 1:
The isolation structure serves multiple functions simultaneously: it provides electrical isolation between adjacent bumps, acts as an etch stop layer during manufacturing, and contributes to mechanical support. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity while maintaining improved reliability.
Solution Approach 2:
The patent specifies that the insulating material should have a dielectric constant less than 3.5 (low-k material), and defines specific thickness ranges for the isolation structure and conductive layers. By optimizing these parameters, the isolation structure achieves effective electrical isolation and mechanical support with minimal added complexity.
3Ease of manufacture
If conventional isolation structures are used, then manufacturing is simpler, but parasitic capacitance increases
Solution Approach 1:
The patent specifies using low-k dielectric material with a dielectric constant less than 3.5 for the isolation structure. This parameter change significantly reduces parasitic capacitance between adjacent bump electrodes compared to conventional isolation materials, while the isolation structure can still be formed using standard semiconductor manufacturing techniques.
Solution Approach 2:
The isolation structure uses composite material systems combining low-k dielectric material with conductive layers (such as copper or aluminum). This composite approach reduces parasitic capacitance while maintaining electrical connectivity where needed and providing mechanical support, achieving better performance than conventional homogeneous isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and mechanical strength of bump electrodes, reducing the likelihood of failure and maintaining low parasitic capacitance, thus addressing the challenges posed by the miniaturization of semiconductor device bumps.
Implementation Method 1
an isolation structure made of low-k dielectric material, functioning as an etch stop layer and improving mechanical strength while maintaining low parasitic capacitance
Implementation Method 2
conductive layers formed using techniques like PVD and CVD
Implementation Method 3
conductive layers formed using techniques like PVD and CVD
Data Source
AI summary
A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.