Low-K Chip Packaging via Redistribution Wiring and Metal Posts
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Solution Overview
Problem
Current low-k chip packaging methods, such as wire bonding and conventional flip-chip bonding, lead to stress concentration and fracture of the dielectric layer, while non-flow underfill in flip-chip packaging results in poor bonding and cavities, causing reliability issues and high costs.
Innovation Solution
A method involving direct flip-chip mounting on a bearer wafer, followed by metal redistribution wiring and metal posts to alleviate stress, combined with film encapsulation and BGA bump formation, reduces stress on the chip area and integrates wafer-level packaging techniques to lower costs and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip bonding or wire bonding is used for low-k chip packaging, then the packaging process can be completed, but stress concentration occurs at the chip electrodes causing fracture of the dielectric layer and chip failure
Solution Approach 1:
The patent segments the stress path by introducing intermediate structures (redistribution layers and metal posts) between the chip electrodes and the external connections. This segmentation distributes the stress across multiple interfaces and structures rather than concentrating it at the chip electrodes, thereby preventing dielectric layer fracture while maintaining packaging reliability
Solution Approach 2:
The patent introduces intermediary structures including redistribution layers and metal posts that act as stress mediators. These intermediaries absorb and redistribute the mechanical stress generated during packaging, protecting the fragile dielectric layer from direct stress concentration while enabling successful flip-chip bonding
2Strength
If non-flow underfill is applied in flip-chip packaging to reduce stress, then stress redistribution is achieved, but poor bonding occurs and cavities form in the underfill after curing
Solution Approach 1:
The patent extracts the underfill material from the bonding interface area, applying it only in peripheral regions rather than filling the entire space between chip and substrate. This extraction prevents underfill from interfering with the bonding process while still providing stress redistribution functionality in the critical bonding zones
Solution Approach 2:
The patent applies different underfill configurations to different regions: no underfill at the bonding interface for optimal bonding quality, and selective underfill in peripheral areas for stress management. This local differentiation ensures both high bonding quality and adequate stress distribution without cavity formation
3Reliability
If non-flow underfill with reflow flux is used to improve wetting, then solder balls can bond to bonding pads, but the process becomes complex and cost increases
Solution Approach 1:
The patent replaces the complex non-flow underfill with reflow flux system with a simpler, disposable-like approach using standard underfill materials applied in controlled patterns. This eliminates the need for specialized reflow flux formulations and complex curing processes while achieving adequate bonding through proper underfill placement and conventional reflow techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents chip failures from stress concentration, ensures reliable bonding, reduces packaging costs, and simplifies the encapsulation process by using film attachment techniques, resulting in high-reliability BGA packages for low-k chips.
Implementation Method 1
attaching a temporary strippable film to the bearer wafer, and mounting the chips obtained in step 1 one by one to the bearer wafer attached with the temporary strippable film
Implementation Method 2
attaching a film layer I to the bearer wafer for encapsulation after flip-chip mounting of the chips, bonding a supporting wafer to the film layer I in the encapsulation process, and then curing the film layer I
Implementation Method 3
forming single-layer or multi-layer metal redistribution wiring on the surface of the film layer I and the chips by photo-lithography, sputtering, or electroplating
Implementation Method 4
forming metal posts at the terminals of metal redistribution wires by photo-lithography or electroplating
Implementation Method 5
attaching a film layer II to the surface of the restructured wafer having the metal posts for encapsulation, curing the package
Implementation Method 6
removing the film material on the top of the metal posts by laser ablation, to form complete or partial openings on the metal posts and expose the top of the metal posts out of the film layer II
Implementation Method 7
forming BGA bumps on the metal layer by printing or bumping
Data Source
AI summary
Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (2-10).