Low-k Contact Etch Stop Layer for FinFET RC Delay Reduction
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Solution Overview
Problem
Existing FinFET source/drain contact formation techniques are not entirely satisfactory for smaller feature sizes, leading to increased complexity and unsatisfactory performance in semiconductor devices.
Innovation Solution
A method for fabricating semiconductor devices involves forming a gate stack over a channel region, trimming gate spacers, depositing a contact etch stop layer, and forming a source/drain contact, which reduces capacitance and resistance by increasing the thickness of gate spacers and using a low-k dielectric material for the contact etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact formation techniques are used, then manufacturing process is simpler, but device performance is unsatisfactory due to high parasitic capacitance and RC delay
Solution Approach 1:
The contact formation process is segmented into multiple stages: forming gate spacers with specific thickness, selectively removing portions of gate spacers, depositing contact etch stop layer, and forming source/drain contacts. This segmentation allows optimization of each stage to reduce parasitic capacitance while maintaining manufacturing feasibility.
Solution Approach 2:
Different regions of the gate spacer are treated differently - portions adjacent to source/drain regions are selectively removed to reduce capacitance, while other portions are retained to maintain structural integrity. The contact etch stop layer is deposited only in specific locations to prevent electrical shorts locally without affecting the entire structure.
2Reliability
If gate spacer thickness is increased to reduce capacitance, then parasitic capacitance decreases, but manufacturing precision requirements increase
Solution Approach 1:
Gate spacers are formed with a predetermined greater thickness before any selective removal. This preliminary action ensures that even after selective portions are removed, sufficient thickness remains in critical areas to prevent electrical shorts, while allowing capacitance reduction in non-critical areas.
Solution Approach 2:
The gate spacer thickness parameter is optimized to be greater than conventional thickness. This parameter change reduces parasitic capacitance between gate and source/drain contacts. The selective removal process then modifies local thickness to achieve the desired capacitance reduction while maintaining reliability.
3Reliability
If contact etch stop layer is deposited to prevent electrical shorts, then reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
A contact etch stop layer is deposited as an intermediary layer between the gate spacer and source/drain contacts. This thin layer acts as a barrier to prevent electrical shorts while allowing the manufacturing process to continue with standard contact formation techniques, minimizing the increase in process complexity.
4Speed
If RC delay is reduced to enhance signal speed, then device performance improves, but process complexity increases
Solution Approach 1:
The physical parameters of the contact structure are changed - gate spacer thickness is increased and selectively modified, and contact etch stop layer is deposited. These parameter changes directly reduce RC delay by reducing parasitic capacitance, thereby enhancing signal speed while using established fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by reducing parasitic capacitance and RC delay, enhancing signal speed without causing electrical shorts or reliability issues.
Implementation Method 1
using a low-k dielectric material for the contact etch stop layer
Data Source
AI summary
Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.