Area-Selective Low-k Dielectric Deposition for Via Alignment
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Solution Overview
Problem
Existing electronic device fabrication methods face challenges in aligning features between layers, leading to issues like shorting and capacitive coupling due to via misalignment, which become more pronounced as transistor sizes decrease, and conventional area-selective deposition methods are limited to forming high-k dielectric materials.
Innovation Solution
Implementing area-selective deposition techniques to form supplemental dielectric layers with low-k dielectric materials by using passivation and catalyst layers to selectively deposit dielectric layers on conductive layers, achieving alignment and reducing capacitive coupling through diagonal spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form dielectric layers, then high-k dielectric materials can be formed, but alignment between vias and conductive lines deteriorates leading to shorting and capacitive coupling
Solution Approach 1:
A passivation layer is formed on the conductive layer before forming the supplemental dielectric layer. This preliminary passivation action prevents the catalyst layer from forming on the conductive layer, ensuring that the supplemental dielectric layer will only form on the ILD layer surface, thereby guaranteeing proper alignment and preventing shorting between vias and conductive lines
Solution Approach 2:
A catalyst layer is introduced as an intermediary between the passivation layer and the supplemental dielectric layer. The catalyst layer selectively forms on the passivation layer and induces the formation of the low-k dielectric material, enabling area-selective deposition that maintains alignment precision while forming the supplemental dielectric layer
2Productivity
If transistor sizes are decreased to improve device density, then productivity increases, but alignment precision deteriorates leading to increased shorting and capacitive coupling
Solution Approach 1:
The passivation layer is formed in advance on the conductive layer to create a protective barrier. This preliminary action ensures that even as transistor sizes decrease and alignment becomes more critical, the supplemental dielectric layer will form only in the correct location on the ILD layer, maintaining alignment precision regardless of device density
Solution Approach 2:
The passivation and catalyst layers create locally different surface properties: the passivation layer prevents catalyst formation on conductive regions, while the catalyst layer promotes dielectric formation on ILD regions. This local differentiation ensures precise spatial control of dielectric layer formation, maintaining alignment accuracy even at reduced transistor dimensions
3Manufacturing precision
If area-selective deposition is implemented with passivation and catalyst layers, then alignment precision is maintained and capacitive coupling is reduced, but device complexity increases
Solution Approach 1:
The passivation layer and catalyst layer functions are combined in a sequential deposition process where the passivation layer is formed first to prevent catalyst formation on conductive layers, followed by the catalyst layer that induces selective dielectric formation. This merging of protective and catalytic functions in a coordinated sequence achieves precise alignment control while managing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances device performance by reducing shorting and capacitive coupling between vias, maintaining alignment and improving device reliability, even at nanoscale transistor sizes, using low-k dielectric materials.
Implementation Method 1
selectively forming at least one passivation layer on at least one first conductive layer... wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer
Implementation Method 2
selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer
Data Source
AI summary
A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.