Drop Reliability Testing for Low-k Dielectric ICs
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Solution Overview
Problem
Portable electronic devices with low-k or extra low-k dielectric materials in their ICs are prone to cracking and delamination under mechanical stress, making it challenging to ensure the reliability of both top and lower level interconnections during drop tests, as existing testing methods fail to accurately assess the fragility of these materials.
Innovation Solution
A drop reliability testing system that includes a test chip with metallization layers and conductive redistribution layers, where a daisy chain test circuit monitors real-time resistance changes during a drop test to detect delamination or cracking in low-k or ELK dielectric materials, using a JEDEC-standardized deceleration profile to simulate the mechanical shock of a drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k or extra low-k dielectric materials are used in ICs to improve electrical performance, then the electrical performance is improved, but the materials become more fragile and prone to cracking and delamination under mechanical stress
Solution Approach 1:
The patent changes the mechanical properties of the dielectric structure by introducing a stress relief layer with different mechanical characteristics (lower Young's modulus) between the rigid low-k dielectric layer and the substrate. This parameter change in the intermediate layer absorbs mechanical stress and prevents cracking in the low-k dielectric material, resolving the contradiction between electrical performance and mechanical strength.
2Ease of manufacture
If existing testing methods are used to assess IC reliability, then the testing process is simple, but they fail to accurately detect delamination or cracking in low-k or ELK dielectric materials
Solution Approach 1:
The patent introduces an intermediary stress relief layer that serves as a mechanical buffer between the substrate and the low-k dielectric layer. This intermediary layer prevents stress concentration and cracking, thereby improving the accuracy of reliability testing by eliminating false failure modes while maintaining testing simplicity.
3Strength
If a stress relief layer with lower Young's modulus is introduced between the low-k dielectric layer and the substrate, then cracking and delamination are reduced, but the device structure becomes more complex
Solution Approach 1:
The patent segments the dielectric structure into distinct functional layers: a rigid low-k dielectric layer for electrical performance and a separate stress relief layer for mechanical protection. This segmentation allows each layer to optimize its specific function, improving crack resistance while keeping the added complexity manageable through clear functional separation.
4Length of moving object
If the low-k dielectric layer is made thinner to reduce device size, then the device dimensions are reduced, but the fragility and susceptibility to cracking increase
Solution Approach 1:
The patent applies beforehand cushioning by placing a stress relief layer beneath the thin low-k dielectric layer before mechanical stress is applied. This pre-positioned cushioning layer absorbs and distributes stress, preventing cracking in the thinned dielectric layer and enabling miniaturization without sacrificing mechanical strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively assesses the reliability of ICs with low-k or ELK materials by detecting short spikes in resistance, indicating potential failures, thereby ensuring the accuracy of reliability tests and prompting redesigns to improve chip durability.
Implementation Method 1
a daisy chain test circuit monitors real-time resistance changes during a drop test to detect delamination or cracking in low-k or ELK dielectric materials
Implementation Method 2
using a JEDEC-standardized deceleration profile to simulate the mechanical shock of a drop
Data Source
AI summary
A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.