Low-k Dielectric Structure With Hardness for Etch-Resistant Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing low-k dielectric materials used in semiconductor devices are soft and porous, leading to issues such as metal line breakage or bridging during processing, due to their inability to withstand etching and ashing processes effectively.
Innovation Solution
A low-k dielectric structure with sufficient hardness is developed, comprising a carbon-rich dielectric layer with a higher carbon atom content and a lower oxygen atom content, which is formed using a silicon-containing heterocyclic compound precursor. This structure has a dielectric constant of less than 3.2 and a Young's modulus greater than 30 GPa, enhancing its resistance to etching damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to reduce RC delay, then the dielectric constant is reduced, but the material becomes soft and porous leading to metal line breakage or bridging
Solution Approach 1:
The patent changes the chemical composition parameters of the dielectric material by incorporating silicon-containing heterocyclic compounds with specific molecular structures (five-membered or six-membered rings containing silicon and heteroatoms). This compositional parameter change achieves a dielectric constant of less than 3.2 while simultaneously providing sufficient hardness (Young's modulus greater than 30 GPa) to resist etching damage and prevent metal line defects.
Solution Approach 2:
The invention creates a composite dielectric material system that combines silicon-containing heterocyclic compounds with oxygen-containing compounds. This composite approach allows the material to exhibit both low dielectric constant properties (k < 3.2) and high mechanical strength (Young's modulus > 30 GPa), resolving the contradiction between softness and hardness by synergistically combining different chemical components.
2Reliability
If low-k dielectric materials are used to reduce RC delay, then the dielectric constant is reduced, but the material becomes porous leading to metal line breakage or bridging
Solution Approach 1:
The patent modifies the molecular structure parameters of the dielectric material by using silicon-containing heterocyclic compounds with specific ring structures. This structural parameter change results in a denser material packing that reduces porosity while maintaining low dielectric constant (k < 3.2), thereby preventing metal line breakage or bridging during subsequent processing steps.
3Reliability
If existing low-k dielectric materials are used, then RC delay is reduced, but the materials are not satisfactory in all respects particularly during conductive material fabrication
Solution Approach 1:
The invention optimizes the chemical parameters of the dielectric material by selecting silicon-containing heterocyclic compounds with specific molecular weights and ring structures. These parameter optimizations enable the material to withstand standard etching and ashing processes used in conductive material fabrication, improving reliability during processing without requiring additional complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed low-k dielectric structure effectively reduces RC delay in semiconductor devices while providing sufficient hardness to resist etching damage, thereby improving the reliability and performance of the devices.
Implementation Method 1
A silicon-containing heterocyclic compound precursor and an oxygen-containing compound precursor are introduced into a process chamber in a predetermined flow rate ratio, so as to form a low-k dielectric structure on the substrate
Implementation Method 2
Low-k dielectric materials are used to reduce the RC delay. The low-k dielectric structure has a dielectric constant of less than 3.2
Data Source
AI summary
A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer.