Low-k Dielectric Layer Formation via Silicon Precursor Processing
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to reduce process margins while maintaining mechanical strength and minimizing parasitic capacitance, particularly in forming low-k dielectric layers with high integration density and performance.
Innovation Solution
A method involving the use of a silicon precursor with specific chemical formulations, such as those represented by Chemical Formula 1, to form a dielectric layer with a controlled ratio of Si—CH3 to Si—O bonding units and porogen groups, which undergo energy treatment to create a porous structure with a low dielectric constant and high mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a low-k dielectric layer is formed to reduce parasitic capacitance, then the dielectric constant is reduced, but the mechanical strength deteriorates
Solution Approach 1:
The patent employs porous low-k dielectric materials with controlled pore structures to achieve low dielectric constant (k<3) while maintaining mechanical strength. The porous structure reduces parasitic capacitance between interconnection lines, and the patent specifically addresses mechanical strength deterioration by controlling pore size, distribution, and using appropriate filling materials that provide structural support while maintaining low-k properties
Solution Approach 2:
The patent uses composite dielectric materials combining organic and inorganic components, or multiple dielectric layers with different k-values, to achieve both low parasitic capacitance and adequate mechanical strength. The composite structure allows optimization of electrical properties (low-k) while the reinforcing phases or interfacial structures provide mechanical support
2Productivity
If process margin is reduced to achieve higher integration density, then device performance is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs parameter changes in the dielectric material properties (dielectric constant, mechanical strength, stress characteristics) to enable process optimization. By selecting dielectric materials with specific parameter combinations (low-k values with adequate mechanical strength), the process window is expanded, allowing higher integration density while maintaining manufacturing precision through better process control
3Object-generated harmful factors
If dielectric constant is reduced to minimize parasitic capacitance, then interconnection performance is improved, but mechanical robustness deteriorates
Solution Approach 1:
The patent uses porous dielectric structures where the pore network reduces dielectric constant (minimizing parasitic capacitance) while the patent specifically addresses mechanical robustness by controlling pore morphology, size distribution, and using appropriate pore fillers that provide mechanical reinforcement without significantly increasing the dielectric constant
Solution Approach 2:
The patent employs composite dielectric systems combining low-k materials with mechanical reinforcement phases, or multi-layer structures where different materials provide complementary functions (electrical performance vs. mechanical support), achieving both low parasitic capacitance and adequate mechanical robustness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a dielectric layer with a dielectric constant of 2.2-3 and Young's modulus of 6 GPa-15 GPa, effectively reducing parasitic capacitance and supporting interconnection lines while maintaining mechanical robustness.
Implementation Method 1
forming a preliminary dielectric layer on a substrate using a silicon precursor
Implementation Method 2
performing an energy treatment on the preliminary dielectric layer to form the dielectric layer
Data Source
AI summary
A method of forming a dielectric layer includes forming a preliminary dielectric layer on a substrate using a silicon precursor and performing an energy treatment on the preliminary dielectric layer to form a dielectric layer. In the dielectric layer, a ratio of Si—CH3 bonding unit to Si—O bonding unit ranges from 0.5 to 5.