Low-k Dielectric PECVD for Lower RC Delay and Stronger Breakdown
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Solution Overview
Problem
Existing semiconductor technologies face challenges in reducing resistive-capacitive (RC) delay in signal propagation due to high parasitic capacitance between conductive interconnects, which is exacerbated by the use of conventional dielectric materials with higher dielectric constants.
Innovation Solution
The formation of a low-k dielectric layer using plasma-enhanced chemical vapor deposition (PECVD) with diethoxymethylsilane and oxygen precursors, enhancing Si—C—Si bonding and reducing Si—CH3 bonding to achieve a dielectric constant of 3.3 or lower, thereby decreasing parasitic capacitance and improving mechanical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials with higher dielectric constants are used, then mechanical strength and ease of manufacture are improved, but parasitic capacitance increases leading to higher RC delay
Solution Approach 1:
The patent changes the dielectric constant parameter by forming a low-k dielectric layer with k≤3.3 using PECVD with specific precursor ratios (mDEOS to carrier gas ≤0.2), transforming the dielectric material properties to reduce parasitic capacitance and RC delay while maintaining mechanical integrity
Solution Approach 2:
The patent creates a composite dielectric structure with a low-k dielectric layer (k≤3.3) formed by PECVD containing specific bonding configurations (Si-C-Si and Si-CH3), combining multiple material characteristics to achieve both low parasitic capacitance and sufficient mechanical strength
2Object-generated harmful factors
If low-k dielectric materials are used to reduce parasitic capacitance, then RC delay is reduced, but mechanical robustness may be compromised
Solution Approach 1:
The patent optimizes the dielectric constant parameter to k≤3.3 (extreme low-k range) while controlling bonding composition through PECVD process parameters, achieving a balance between low parasitic capacitance and mechanical robustness required for advanced semiconductor devices
Solution Approach 2:
The patent creates specific local bonding structures (Si-C-Si and Si-CH3 configurations) within the low-k dielectric layer through controlled PECVD deposition, providing localized mechanical strength while maintaining overall low dielectric constant for reduced capacitance
3Reliability
If PECVD process with specific precursor ratios is used to form low-k dielectric, then dielectric constant is reduced to 3.3 or lower, but process complexity increases
Solution Approach 1:
The patent achieves extreme low-k (k≤3.3) by precisely controlling the mDEOS precursor gas flow rate ratio to carrier gas (≤0.2) in PECVD, transforming the dielectric material properties through parameter optimization while maintaining process feasibility
Solution Approach 2:
The patent replaces traditional dielectric formation methods with PECVD process control, using chemical vapor deposition with specific precursor ratios to achieve low-k properties, substituting mechanical/material selection approaches with chemical process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-k dielectric layer reduces parasitic capacitance by 6-7%, enhances device speed, and increases voltage breakdown and time-dependent dielectric breakdown resistance, making it suitable for advanced semiconductor manufacturing.
Implementation Method 1
The formation of a low-k dielectric layer using plasma-enhanced chemical vapor deposition (PECVD) with diethoxymethylsilane and oxygen precursors
Implementation Method 2
The formation of a low-k dielectric layer using plasma-enhanced chemical vapor deposition (PECVD) with diethoxymethylsilane and oxygen precursors
Data Source
AI summary
Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.