Semiconductor Gate Contacts on Low-k Liners for Capacitance Reduction
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Solution Overview
Problem
Forming source and drain regions with desired characteristics in nanostructure transistors is challenging, particularly in semiconductor devices with increased computing power requirements.
Innovation Solution
Incorporating low-k dielectric layers laterally between the gate contact and source/drain contact to reduce capacitance, combined with an isotropic etching step for simplified and efficient device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If source and drain regions are formed in nanostructure transistors, then computing power is increased, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the gate contact formation process by introducing a low-k dielectric liner layer between the gate electrode and the gate contact. This segmentation allows the gate contact to be formed in separate stages: first forming the gate electrode, then depositing the low-k dielectric liner, and finally forming the gate contact through the liner. This resolves the manufacturing difficulty by breaking down the complex process into manageable steps while maintaining the high computing power benefits of nanostructure transistors.
Solution Approach 2:
The low-k dielectric liner acts as an intermediary layer between the gate electrode and the gate contact. This intermediary serves multiple functions: it provides a platform for gate contact formation, reduces parasitic capacitance, and enables selective etching processes. By introducing this intermediary element, the patent simplifies the overall manufacturing process while maintaining device performance.
2Device complexity
If gate contact is formed directly on gate electrode, then manufacturing process is simplified, but capacitance between gate and source/drain contacts increases
Solution Approach 1:
The low-k dielectric liner serves as an intermediary layer that reduces parasitic capacitance between the gate contact and source/drain contacts. This thin dielectric layer (typically 1-5 nm) provides electrical isolation while allowing the gate contact to be formed through it via selective etching. The intermediary nature of this layer resolves the contradiction by maintaining manufacturing simplicity while improving electrical performance.
Solution Approach 2:
The patent changes the dielectric parameter by introducing a low-k material with dielectric constant k < 3.5 (preferably k < 2.5) between the gate electrode and gate contact. This parameter change significantly reduces parasitic capacitance compared to conventional high-k dielectric materials, thereby improving device reliability while maintaining a relatively simple manufacturing process.
3Reliability
If low-k dielectric liner is added, then capacitance is reduced, but manufacturing steps increase
Solution Approach 1:
The patent merges the low-k dielectric liner deposition with the existing gate contact formation process. The liner is deposited conformally over the gate electrode, and the gate contact is formed through a single etching step that penetrates the liner. This merging approach minimizes additional manufacturing steps while achieving capacitance reduction, as the liner formation is integrated into the standard gate contact fabrication sequence.
Solution Approach 2:
The low-k dielectric liner is deposited in a self-aligned manner, where the liner automatically conforms to the gate electrode shape and position. This self-alignment eliminates the need for separate alignment and patterning steps, as the liner naturally forms where needed based on the underlying gate electrode topology. The self-service nature of this process reduces manufacturing complexity while achieving the desired capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances transistor performance by reducing capacitance and enabling good operation without failure, while simplifying the manufacturing process.
Implementation Method 1
one or more low-k dielectric layers which reduces a capacitance between a gate contact and a source/drain contact
Data Source
AI summary
A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.