Low-k Metal Gate Isolation for Lower Resistance and Capacitance
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Solution Overview
Problem
Current semiconductor technologies result in metal conductive features with higher resistance and capacitance due to extending through high-k or low-k metal contact etch stop layers, leading to increased dimensions and suboptimal device performance.
Innovation Solution
Employing sacrificial self-aligned contact (SAC) and sacrificial metal contact etch stop layers (M-CESL) to form conductive features with reduced thickness and increased width, followed by replacing these layers with low-k materials to reduce capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal conductive features are extended through high-k or low-k metal contact etch stop layers, then the conductive features can be formed to connect interlayer dielectric, but the resistance and capacitance increase
Solution Approach 1:
The patent divides the metal conductive feature into multiple segments: a first portion embedded in the low-k dielectric layer and a second portion extending into the interlayer dielectric layer. This segmentation allows each portion to be optimized independently - the first portion can be wider to reduce resistance while the second portion connects to the metal contact, thereby reducing overall resistance and capacitance while maintaining proper electrical connection.
Solution Approach 2:
The patent applies local quality by making different portions of the metal conductive feature have different dimensions. Specifically, the first portion embedded in the low-k dielectric layer is made wider than the second portion, creating locally optimized electrical properties where the wider section reduces resistance in the high-capacitance region while the narrower section maintains proper connection geometry.
2Object-affected harmful factors
If the conductive feature width is increased to reduce resistance, then the resistance decreases, but the device dimension increases
Solution Approach 1:
The conductive feature is segmented into portions with different widths - the first portion in the low-k dielectric layer is wider to reduce resistance, while the second portion has reduced width. This allows the device to benefit from lower resistance without proportionally increasing the overall device footprint, as the wider section is confined to the localized region where it provides maximum electrical benefit.
Solution Approach 2:
The patent optimizes the conductive feature geometry by varying dimensions across different vertical layers. The first portion has greater lateral dimensions when embedded in the low-k dielectric layer, while the second portion transitions to smaller dimensions. This dimensional variation across layers reduces resistance without proportionally increasing the planar device footprint.
3Object-affected harmful factors
If sacrificial layers are used to form conductive features, then the conductive features achieve reduced thickness and increased width, but additional fabrication steps are required
Solution Approach 1:
The patent employs preliminary action by forming sacrificial self-aligned contact (SAC) layers and sacrificial metal contact etch stop (M-CESL) layers before creating the final conductive features. These sacrificial structures are prepared in advance with specific geometries, then used as templates to define the precise shape and dimensions of the metal conductive features, enabling reduced thickness and increased width optimization.
Solution Approach 2:
The sacrificial SAC and M-CESL layers serve as intermediary structures that facilitate the formation of the optimized conductive features. These temporary structures mediate between the fabrication process and the final device geometry, allowing precise control over the conductive feature dimensions (reduced thickness, increased width) while enabling selective removal after the metal features are formed.
Data Source
AI summary
Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.