Low-k Gate Side Insulating Layer for Reduced RC Delay
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Solution Overview
Problem
As semiconductor devices become more integrated and miniaturized, parasitic capacitance between the gate electrode and contact plugs leads to RC delays, which existing technologies have not adequately addressed.
Innovation Solution
The semiconductor device design includes a gate structure with a U-shaped gate dielectric layer surrounding the gate barrier layer and gate side insulating layers, which are vertically aligned with the gate dielectric layer, reducing parasitic capacitance and increasing the conductivity of the gate electrode by forming spacers on both side surfaces of the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode volume is increased to improve conductivity, then the parasitic capacitance between gate electrode and contact plugs increases, but this increases RC delay
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions around the gate electrode. The gate dielectric layer uses a first dielectric material, while the gate side insulating layers use a second dielectric material with lower capacitance characteristics. This local differentiation allows the gate electrode to maintain sufficient volume for conductivity while reducing parasitic capacitance in critical regions near contact plugs.
Solution Approach 2:
The insulating structure is segmented into multiple distinct layers: a gate dielectric layer directly surrounding the gate electrode, and separate gate side insulating layers positioned between the gate electrode and contact plugs. This segmentation allows independent optimization of each layer's properties - the gate dielectric can provide necessary electrical isolation while the gate side insulating layers specifically address parasitic capacitance reduction.
2Productivity
If the degree of integration is increased to improve productivity, then parasitic capacitance between gate electrode and contact plugs increases, but this increases RC delay
Solution Approach 1:
As integration density increases, the patent employs gate side insulating layers with specific low-capacitance dielectric materials in the regions between gate electrodes and contact plugs. This localized application of specialized materials allows high integration without proportionally increasing parasitic capacitance, maintaining signal integrity despite reduced spacing.
3Productivity
If miniaturization is pursued to improve productivity, then the volume of gate electrode is reduced to increase integration density, but this decreases conductivity
Solution Approach 1:
The patent uses dielectric materials with different capacitance characteristics in different locations. The gate dielectric layer material is selected to provide appropriate electrical properties for the gate structure, while gate side insulating layer materials are specifically chosen with lower capacitance to reduce parasitic effects, enabling miniaturization without sacrificing conductivity.
Solution Approach 2:
The insulating structure comprises composite materials - a gate dielectric layer made of a first dielectric material and gate side insulating layers made of a second dielectric material. This composite approach allows optimization of each material's properties for its specific function, maintaining conductivity while reducing parasitic capacitance in the miniaturized structure.
Data Source
AI summary
A semiconductor device includes a gate structure crossing an active region of a substrate, and spacers formed on both side surfaces of the gate structure. The gate structure includes an interfacial insulating layer formed on the substrate, a gate dielectric layer formed on the interfacial insulating layer, a gate barrier layer and gate side insulating layers formed on the gate dielectric layer, and a gate electrode on the gate barrier layer. The gate dielectric layer is in contact with inner side surfaces of the spacers, and has a U-shaped longitudinal cross-sectional shape to surround a lower surface and some portions of side surfaces of the gate barrier layer. The gate side insulating layers surround outer side surfaces of the gate barrier layer.