Low-K Gate Spacer Layout for FinFET Contact RC Reduction
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Solution Overview
Problem
Existing FinFET source/drain contact formation techniques are not entirely satisfactory for smaller feature sizes, leading to increased complexity and unsatisfactory performance in semiconductor devices.
Innovation Solution
A method for fabricating semiconductor devices involving forming a gate stack over a channel region, epitaxial source/drain features, trimming gate spacers, depositing a contact etch stop layer, and forming source/drain contacts, which reduces capacitance and resistance by modifying the thickness and dielectric constant of gate spacers and contact etch stop layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact formation techniques are used for smaller feature sizes, then manufacturing simplicity is maintained, but device performance becomes unsatisfactory due to increased parasitic capacitance and RC delay
Solution Approach 1:
The gate spacer is divided into two distinct portions: a first portion with greater thickness and a second portion with lesser thickness. This segmentation allows different regions to serve different functions - the thicker first portion provides mechanical support and isolation, while the thinner second portion reduces parasitic capacitance. The contact etch stop layer is selectively deposited only on the second portion, further segmenting the structure to optimize electrical performance without unnecessarily complicating the entire manufacturing process.
Solution Approach 2:
The contact etch stop layer is deposited selectively only on the second portion of the gate spacer, not the entire structure. This local quality approach applies the low-k dielectric material precisely where needed - on the thinner second portion that is adjacent to the source/drain contact - to reduce parasitic capacitance in the critical region while avoiding unnecessary processing of other areas, thus improving performance without proportionally increasing manufacturing complexity.
2Speed
If gate spacer thickness is reduced to reduce parasitic capacitance, then signal speed improves, but electrical shorts and reliability issues may occur
Solution Approach 1:
The gate spacer is segmented into a thicker first portion and a thinner second portion. The thinner second portion reduces parasitic capacitance to improve signal speed, while the thicker first portion maintains sufficient thickness to prevent electrical shorts and ensure mechanical integrity. This segmentation allows the structure to simultaneously achieve both speed improvement and reliability maintenance.
Solution Approach 2:
The contact etch stop layer is deposited beforehand on the second portion of the gate spacer to provide electrical isolation and prevent shorts. This prior cushioning measure ensures that even when the gate spacer thickness is reduced to improve signal speed, the reliability is maintained through the protective low-k dielectric layer that prevents electrical breakdown and short circuits.
Data Source
AI summary
Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.