Low-K Gate Spacer Structure for FinFET RC Delay Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in forming low-k features in FinFET devices due to the increasing complexity of three-dimensional designs, which affect device performance and reliability.
Innovation Solution
The implementation of a surface modification layer with varying nitrogen and oxygen concentrations, and a low-k gate spacer layer formed using Atomic Layer Deposition (ALD) processes, along with a multi-layer gate spacer structure, to protect and enhance the low-k features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deposition processes are used to form dielectric layers, then the manufacturing process is simpler, but the dielectric constant cannot be sufficiently reduced and nitrogen concentration control is poor
Solution Approach 1:
The patent applies parameter changes by systematically varying deposition temperature, nitrogen source flow rates, and precursor ratios during ALD processes to achieve precise control over nitrogen concentration and dielectric constant. The method transitions from conventional fixed-parameter deposition to dynamic parameter adjustment, where nitrogen concentration is controlled as a variable parameter ranging from 0-50 atomic percent to optimize both RC delay reduction and process control.
Solution Approach 2:
The patent employs composite materials by creating dielectric layers with graded nitrogen concentrations (0-50 atomic percent) within the same layer or across multiple layers. This composite approach combines regions of different nitrogen content to achieve optimized dielectric constants while maintaining mechanical integrity and process control, effectively resolving the contradiction between performance and complexity.
2Reliability
If higher nitrogen concentrations are used to reduce dielectric constant, then RC delay is reduced, but etch selectivity and protection of low-k features deteriorate
Solution Approach 1:
The patent applies local quality by creating spatially varying nitrogen concentrations within dielectric layers, where different regions have different nitrogen content optimized for their specific functions. Low-k regions (higher nitrogen) provide RC delay reduction, while protected regions (lower nitrogen) maintain etch resistance. This local differentiation resolves the contradiction by allowing high nitrogen concentration only where needed for dielectric performance.
Solution Approach 2:
The patent segments the dielectric structure into multiple layers or regions with different nitrogen concentrations (0-50 atomic percent). This segmentation allows the structure to simultaneously achieve low dielectric constant in nitrogen-rich regions and high etch selectivity in nitrogen-poor regions, eliminating the trade-off between RC delay reduction and feature protection.
3Manufacturing precision
If conventional CVD processes are used, then deposition speed is faster, but conformal coverage and nitrogen concentration control on three-dimensional structures are insufficient
Solution Approach 1:
The patent applies periodic action by using alternating precursor pulses in the ALD process, where nitrogen-containing precursors and silicon-based precursors are deposited in sequential cycles. This periodic deposition ensures complete surface coverage at each step while maintaining controlled nitrogen concentration, achieving conformal coverage on three-dimensional FinFET structures with precise compositional control despite slower overall deposition rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the dielectric constant of the semiconductor device, lowering resistance-capacitance delay and enhancing device performance by providing better protection against subsequent processing.
Implementation Method 1
A surface modification layer is formed using an Atomic Layer Deposition (ALD) process
Data Source
AI summary
Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.