Low-k Gate Sidewall Spacers for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor integrated circuits shrink, parasitic capacitance between gate stacks and source/drain contacts increases, leading to decreased switching speed, increased power consumption, and coupling noise due to reduced spacing, which existing technologies have not adequately addressed.
Innovation Solution
The formation of a sidewall spacer with a reduced dielectric constant, achieved by using a porous low-k dielectric material or a doped spacer layer, is introduced between the gate stack and source/drain contact to mitigate parasitic capacitance. This is done by depositing a low-k precursor and a porogen, followed by curing to create voids in the spacer layer, or by incorporating dopants like boron or phosphorus to reduce the dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If spacing between gate stacks is reduced to increase functional density, then production efficiency increases, but parasitic capacitance increases causing decreased switching speed and increased power consumption
Solution Approach 1:
A sidewall spacer is introduced as an intermediary structure between the gate stack and source/drain contact. This spacer acts as a mediator that reduces parasitic capacitance coupling between adjacent features, thereby maintaining switching speed performance even when spacing is reduced for higher functional density.
Solution Approach 2:
The dielectric constant of the spacer material is changed from conventional values to a reduced dielectric constant (low-k material). This parameter change directly reduces the parasitic capacitance formed between the gate stack and source/drain contact, counteracting the capacitance increase that would normally result from reduced spacing.
2Productivity
If spacing between gate stacks is reduced to increase functional density, then production efficiency increases, but power consumption increases due to increased parasitic capacitance
Solution Approach 1:
The sidewall spacer serves as a dielectric intermediary that reduces parasitic capacitance, thereby reducing the energy required for switching operations. This allows high-density integration without proportionally increasing power consumption.
Solution Approach 2:
By changing the dielectric constant parameter of the spacer material to a lower value, the parasitic capacitance is reduced, which directly reduces the energy consumption associated with charging and discharging these parasitic capacitances during switching operations.
3Ease of manufacture
If conventional spacer material is used, then manufacturing is simpler, but parasitic capacitance is higher reducing circuit performance
Solution Approach 1:
The dielectric constant parameter of the spacer material is changed to a lower value (low-k material). This parameter change reduces parasitic capacitance and improves circuit performance while the patent describes deposition processes that are compatible with existing manufacturing techniques.
Solution Approach 2:
The patent employs composite material structures for the sidewall spacer, combining low-k dielectric materials with other functional layers. This composite approach achieves both the electrical performance benefits of low-k materials and the manufacturing compatibility required for practical implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced dielectric constant of the spacer layer decreases parasitic capacitance, enhancing switching speed, reducing power consumption, and minimizing transient events like logic glitches, thereby improving the performance of integrated circuits.
Implementation Method 1
A low-k dielectric precursor is cured to form a porous low-k dielectric material
Implementation Method 2
a porous low-k dielectric material... The curing forms a void within the low-k dielectric material
Implementation Method 3
a doped spacer layer... incorporating dopants like boron or phosphorus to reduce the dielectric constant
Data Source
AI summary
Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.