Low K Interconnect Doping for RC Delay Reduction
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Solution Overview
Problem
The existing interconnect structures in semiconductor technology suffer from large resistance-capacitance (RC) delay due to damage to the Low K inter-dielectric layer during etching, chemical mechanical polishing, and metal deposition processes, leading to increased dielectric constant and impaired electrical performance.
Innovation Solution
A method involving the sequential formation of a semiconductor substrate with a barrier layer, Low K inter-dielectric layer, and cap dielectric layer, followed by etching to form a groove, removing the cap dielectric layer, and doping carbon elements into the Low K inter-dielectric layer to compensate for carbon ion loss, thereby reducing the dielectric constant and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching, CMP, and metal deposition processes are used to form interconnect structure, then the interconnect structure can be formed, but the Low K inter-dielectric layer is damaged causing carbon ion loss and increased dielectric constant
Solution Approach 1:
The patent applies preliminary action by forming a protective cap layer over the Low K inter-dielectric layer before the etching, CMP, and metal deposition processes. This cap layer prevents carbon ion loss and damage to the Low K layer during subsequent processing steps, thereby maintaining the dielectric constant and electrical performance without requiring changes to the standard interconnect formation工艺流程
Solution Approach 2:
The cap layer serves as an intermediary protective element between the processing environment (etching plasma, CMP slurry, metal deposition) and the Low K inter-dielectric layer. It absorbs or shields harmful effects during processing, then is removed afterward to reveal the intact Low K layer with preserved electrical properties
2Reliability
If the dielectric constant of Low K inter-dielectric layer is reduced to decrease capacitance, then RC delay is reduced, but the Low K layer becomes more susceptible to damage during processing
Solution Approach 1:
The cap layer is formed in advance over the Low K inter-dielectric layer with optimized dielectric constant, protecting it during subsequent processing steps. This allows the Low K layer to achieve its full capacitance reduction potential without suffering damage that would increase the dielectric constant back to original levels
Solution Approach 2:
The patent optimizes the dielectric constant parameter of the Low K inter-dielectric layer to achieve desired capacitance reduction and RC delay improvement, while simultaneously introducing the cap layer structure to compensate for the increased susceptibility to processing damage that comes with lower dielectric constant materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases the dielectric constant of the Low K inter-dielectric layer, reducing RC delay and enhancing the performance of semiconductor devices by preventing carbon ion loss during the interconnect structure formation.
Implementation Method 1
the carbon element is doped into the Low K inter-dielectric layer by ion implantation or plasma doping
Implementation Method 2
the carbon element is doped into the Low K inter-dielectric layer by ion implantation or plasma doping
Data Source
AI summary
A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.