Self-aligned low-k dielectric planarization via triangular oxide spacer
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Solution Overview
Problem
The existing processes for forming low-k dielectrics in semiconductor devices, such as MRAM, result in a small and insufficient top contact process window and uneven topography due to larger planarization variations, which complicates the integration of emerging memory technologies like MRAM, ReRAM, and FeRAM into back-end-of-line (BEOL) low-K process steps.
Innovation Solution
A method is developed to form a uniform self-aligned low-k layer with a large process window by forming a substrate with distinct regions, depositing a first low-K layer, an oxide layer, and a spacer, followed by etching and cleaning processes to create a triangular-like shaped oxide layer, allowing for the formation of a second low-K layer, thereby addressing the topography challenges and cost issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional spin-on-glass and etch back processes are used for planarization, then the topography is flattened, but the process complexity and cost increase
Solution Approach 1:
The patent forms a planarization layer with a specific triangular-like shaped portion protruding upward before subsequent processing steps. This preliminary shaping action eliminates the need for conventional CMP planarization processes, as the desired planar surface is achieved through the selective removal of the protruding portion in later etching steps, thereby reducing process complexity while maintaining topography uniformity
Solution Approach 2:
The planarization layer is segmented into different regions: a first region over the memory array and a second region over the logic region. The triangular-like shaped portion is selectively formed and removed from specific areas, allowing differential processing that simplifies the overall planarization process while accommodating varying topography requirements across different device regions
2Shape
If CMP process is used to planarize varying heights, then the topography is uniform, but the manufacturing cost increases
Solution Approach 1:
The patent performs preliminary formation of the triangular-like shaped protruding portion during the layer deposition and patterning stages, before the final planarization is needed. This allows the uniform surface to be achieved through selective material removal rather than expensive CMP processing, reducing manufacturing costs while maintaining the required topography uniformity for subsequent BEOL low-k process steps
3Quantity of substance
If low-k layer is deposited over pillar contact with varying heights, then the dielectric layer is formed, but the topography variation increases
Solution Approach 1:
The patent applies different treatments to different regions: the planarization layer with triangular-like shaped portion is specifically formed over the memory array region with pillar contacts, while the logic region receives standard processing. This local quality approach allows the dielectric layer to be formed over varying heights without propagating topography variations, as the protruding portion compensates for height differences in the memory region specifically
4Shape
If conventional planarization processes are used, then the surface is flattened, but the process window for emerging memories is insufficient
Solution Approach 1:
The patent forms the triangular-like shaped protruding portion as a preliminary structure that provides a controlled reference plane for subsequent processing. This preliminary action creates a larger process window for emerging memories by establishing a defined topography that accommodates variations in pillar contact heights, allowing emerging memory technologies with smaller critical dimensions to be integrated into BEOL low-k processes with adequate process margins
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a uniform low-k topography with a large process window, reducing within-wafer and within-die variations, minimizing costs, and maintaining the resistance-capacitance benefits of BEOL low-k, suitable for various semiconductor devices including MRAM, ReRAM, and FeRAM.
Implementation Method 1
etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region
Data Source
AI summary
A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.