Low-K Spacer Design for CMOS Parasitic Capacitance Reduction
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Solution Overview
Problem
The substitution of conventional silicon nitride spacers with low-k spacers in CMOS fabrication processes faces challenges such as increased k-value during high-temperature processes, complications in subsequent fabrication steps, and difficulties in incorporating self-aligned contacts due to damage during reactive ion etch, leading to thickness variations and epitaxy nodules.
Innovation Solution
A semiconductor device design that includes a low-k spacer with vertical and horizontal portions formed on the sidewalls and top surface of gates, respectively, using materials like SiBN, SiCN, and organosilicate glass, which are deposited using specific techniques to maintain dielectric isolation and reduce parasitic capacitance while being resistant to fabrication process-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional silicon nitride spacer is substituted with a low-k spacer in CMOS fabrication processes, then parasitic capacitance between conducting portions is reduced, but the spacer experiences increased k-value during high-temperature processes and suffers damage during reactive ion etch
Solution Approach 1:
The spacer structure is divided into two distinct segments: a lower spacer portion made of silicon nitride that remains after gate patterning, and an upper low-k spacer portion deposited subsequently. This segmentation allows each material to perform its optimal function - the silicon nitride lower portion provides structural integrity and resistance to fabrication damage, while the low-k upper portion reduces parasitic capacitance without being exposed to damaging processes.
Solution Approach 2:
The silicon nitride lower spacer portion is formed first through gate patterning before the low-k upper spacer portion is deposited. This preliminary action ensures that the structural foundation is established and protected from subsequent fabrication processes before the low-k material is added, preventing the low-k portion from experiencing damage during reactive ion etch and high-temperature steps.
2Productivity
If a low-k spacer is used to reduce parasitic capacitance, then circuit performance is improved, but thickness variations and epitaxy nodules occur due to damage during fabrication processes
Solution Approach 1:
The spacer is segmented into lower and upper portions with distinct materials and functions. The lower silicon nitride portion provides a robust, damage-resistant foundation with consistent thickness, while the upper low-k portion can be optimized for capacitance reduction without compromising overall thickness uniformity, as it is not exposed to damaging fabrication processes.
Solution Approach 2:
Different regions of the spacer structure have different material properties optimized for their specific functions. The lower portion near the substrate uses silicon nitride for structural stability and process resistance, while the upper portion uses low-k material for electrical performance. This local differentiation allows each region to maintain optimal quality for its purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces parasitic capacitance and improves semiconductor circuit performance by maintaining low dielectric constant values and ensuring consistent spacer thickness, even after exposure to high-temperature and etching processes, while allowing for successful integration with self-aligned contacts.
Implementation Method 1
A low-k spacer is made from a low-k dielectric material and electrically isolates, insulates, and/or separates conducting portions of a semiconductor device
Implementation Method 2
forming a first low-k spacer portion upon the vertical sidewall of a first gate, forming a second low-k spacer portion upon a vertical sidewall of a second gate
Data Source
AI summary
A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.