Low-k Gate Spacer Etch Protection Layer

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Solution Overview

Problem

Conventional spacer etch processes in semiconductor manufacturing produce unacceptable results in terms of sidewall spacer footing, substrate recess, spacer critical dimension slimming, and dielectric constant variation, particularly when using low-k dielectric materials, leading to increased fringe capacitance between transistor gate and contact or source/drain facets.

Innovation Solution

A method involving a spacer etch process sequence that includes depositing a spacer protection layer on the low-k spacer material, followed by selective and anisotropic etching to retain a sidewall spacer, where the protection layer limits exposure to chemical constituents and reduces depletion of boron (B) or carbon (C), thereby maintaining the dielectric constant within 5% of the initial value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional spacer etch processes are used to remove spacer material, then the spacer etch process can be completed, but the dielectric constant of the low-k spacer material increases due to depletion of B or C constituents

Engineering Contradiction:

Improvespacer etch process completionVSAvoiddielectric constant of low-k spacer material

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

A protection layer is deposited on the spacer material before the etch process. This protection layer acts as an intermediary that limits exposure of the low-k spacer material to chemical constituents during etching, thereby preventing depletion of B or C and maintaining the dielectric constant within 5% of its initial value while still allowing the etch process to proceed

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protection layer is deposited in advance before the spacer etch process begins. This preliminary action prepares the spacer material by creating a protective barrier that will prevent composition changes during the subsequent etching operation, ensuring the dielectric constant remains stable

Inventive Principle:

Principle #10Preliminary action

2Productivity

If conventional spacer etch processes are used, then the spacer etch process can proceed, but unacceptable sidewall spacer footing, substrate recess, and spacer CD slimming occur

Engineering Contradiction:

Improvespacer etch process executionVSAvoidsidewall spacer footing, substrate recess, and spacer CD

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The protection layer serves as a mediator between the etch process and the spacer material, enabling the etch process to proceed while preventing harmful effects on spacer geometry. The protection layer is selectively removed after etching, revealing precisely formed sidewall spacers with correct footing and dimensions

Inventive Principle:

Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If low-k dielectric materials are used as spacer material to counter increased fringe capacitance, then fringe capacitance between gate and contact/facet is reduced, but the spacer etch process causes depletion of B or C leading to increased dielectric constant

Engineering Contradiction:

Improvefringe capacitance between gate and contact/facetVSAvoiddielectric constant of low-k spacer material

Core Design Contradiction:

Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The protection layer acts as an intermediary that allows the low-k spacer material to maintain its low dielectric constant properties during the etch process. By limiting exposure to chemical constituents, the protection layer prevents depletion of B or C that would otherwise increase the dielectric constant, thus preserving the electrical performance benefits of low-k material

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves reduced sidewall spacer footing, substrate recess, and dielectric constant variation, improving the spacer etch process by minimizing CD slimming and maintaining the dielectric constant, thus addressing the issues of fringe capacitance and material composition depletion.

Implementation Method 1

the spacer protection layer limits exposure of the sidewall spacer to one or more chemical constituents in the one or more etching processes

Methodology Applied

Scientific EffectPhysical barrier protection:

Implementation Method 2

performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material

Methodology Applied

Scientific EffectAnisotropic etching:

Data Source

PatentUS9111746B2Method for reducing damage to low-k gate spacer during etching

Publication Date: 2015.08.18 TOKYO ELECTRON LTD

AI summary

A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.