Low-k Spacer Gate Structure for Reduced Parasitic Capacitance
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Solution Overview
Problem
The increasing parasitic capacitance due to high-k sidewall spacers in semiconductor devices slows down transistor switching speed, and alternative low-k materials face challenges such as depletion during processing and mechanical weakness.
Innovation Solution
The method involves forming a sacrificial gate structure with low-k spacers, where a liner layer is deposited on the sacrificial gate electrode's sidewalls, followed by forming a replacement gate structure within a gate cavity laterally defined by the liner layer, and using low-k materials like silicon-carbon-nitride for the spacers to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-k materials are used for sidewall spacers to maintain structural integrity, then spacer strength is improved, but parasitic capacitance increases slowing down transistor switching speed
Solution Approach 1:
The patent changes the dielectric constant parameter of the sidewall spacer material from high-k to low-k (specifically silicon-carbon-nitride with k<6), directly reducing parasitic capacitance and improving transistor switching speed while maintaining adequate mechanical strength through the specific material composition and processing conditions
Solution Approach 2:
The patent uses silicon-carbon-nitride as a composite material that combines the benefits of low dielectric constant (for reduced parasitic capacitance) with sufficient mechanical strength to maintain spacer integrity during processing, resolving the contradiction between electrical performance and structural requirements
2Speed
If low-k materials are used for sidewall spacers to reduce parasitic capacitance, then transistor switching speed is improved, but spacer mechanical strength decreases
Solution Approach 1:
The patent optimizes the composition parameters of the low-k silicon-carbon-nitride material and processing parameters (temperature, pressure, deposition conditions) to achieve the right balance between low dielectric constant and sufficient mechanical strength, transforming a potentially weak material into a viable spacer material
Solution Approach 2:
The patent applies specific local processing conditions and material composition variations to the sidewall spacer region to enhance its mechanical properties locally while maintaining the overall low-k characteristic, ensuring both electrical and mechanical performance requirements are met
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the gate-to-contact capacitance, enabling faster transistor switching speeds while maintaining the structural integrity of the spacers.
Implementation Method 1
forming a liner layer on the exposed sidewalls of the sacrificial gate electrode
Data Source
AI summary
One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.