Low-k Spacer Design for Fringing Field Suppression in NAND Memory
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Solution Overview
Problem
Charge-trapping NAND Flash memory devices beyond the sub-30 nm node face interference issues due to edge fringing fields and programmed charge from adjacent cells, which affect device performance and programming/erasing efficiency.
Innovation Solution
The implementation of low-k spacers between wordlines, which have a relative dielectric constant less than silicon dioxide, suppresses edge fringing fields and confines the electric field within the tunnel dielectric, improving programming/erasing efficiency and reducing interference, allowing for effective operation at nodes as small as 15 nm and below.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is scaled down to sub-30 nm and sub-20 nm nodes, then memory density is improved, but fringing field interference and threshold voltage shifts increase
Solution Approach 1:
The patent changes the dielectric parameter (permittivity) of the material between word lines from conventional high-k values to low-k values. This parameter change directly reduces the capacitance coupling and fringing field effects between adjacent word lines. The low-k dielectric constant reduces the electric field strength in the regions between word lines, thereby reducing interference at the charge trapping sites while maintaining the benefits of charge trapping memory architecture.
Solution Approach 2:
The patent introduces low-k dielectric material as an intermediary substance positioned between adjacent word lines. This intermediary layer has lower permittivity than conventional dielectrics, which reduces the strength of fringing electric fields that extend from one word line to adjacent structures. By placing this low-k material in the region where fringing fields are most problematic, the interference affecting charge trapping sites is minimized without requiring changes to the charge storage mechanism itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-k spacers significantly reduce threshold voltage shifts and interference, enhancing the performance and efficiency of NAND Flash memory cells by suppressing fringing fields and maintaining acceptable interference levels even at half pitches of 15 nm and below.
Implementation Method 1
Edge fringing field due to bias voltages applied to adjacent word lines is a major factor effecting device performance
Implementation Method 2
insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide
Data Source
AI summary
With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge storage structures. The fringing electric fields are suppressed, by the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.