Low-k Spacer Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor device dimensions shrink, parasitic capacitances such as gate-to-contact parasitic capacitance and fringing capacitance significantly impact device performance, particularly in raised source/drain (RSD) devices like ETSOI, FinFET, or nanowire devices, necessitating a reduction in parasitic capacitance to improve AC performance while maintaining low power consumption.
Innovation Solution
A method and structure involving the formation of low-k spacers embedded in an interlayer dielectric (ILD) layer adjacent to raised source/drain regions, with a replacement gate stack including a gate dielectric and conductor layer, to minimize parasitic capacitance and enhance AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to improve integration density, then productivity is improved, but parasitic capacitance increases which worsens AC performance
Solution Approach 1:
The patent applies local quality by implementing low-k dielectric material specifically in the spacer regions adjacent to the gate and source/drain contacts, while other regions of the device use conventional dielectric materials. This localized application of low-k material targets the specific areas where parasitic capacitance has the most impact on AC performance, thereby improving reliability without compromising the benefits of device scaling for productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of low-k spacers effectively reduces parasitic capacitance, thereby improving the AC performance and maintaining low power consumption in semiconductor devices, particularly in RSD devices like ETSOI, FinFET, or nanowire structures.
Implementation Method 1
low-k spacers effectively reduces parasitic capacitance
Data Source
AI summary
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.