Low-k Spacer Formation for Semiconductor Parasitic Capacitance
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Solution Overview
Problem
The high k-value of silicon nitride sidewall spacers in semiconductor devices increases parasitic capacitance, and alternative low-k materials face challenges such as depletion during processing and mechanical weakness, which complicates the fabrication of advanced integrated circuits with densely packed transistors.
Innovation Solution
The method involves forming low-k spacers by creating sacrificial gate structures, defining spacer cavities, and replacing sacrificial spacers with low-k materials like SiCN, SiBN, or SiOCN, which are resistant to processing steps and maintain their properties, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silicon nitride sidewall spacers are used, then mechanical stability is improved, but parasitic capacitance increases due to high k-value
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from high-k (silicon nitride, k≈7-8) to low-k materials (k<4), directly addressing the parasitic capacitance issue while maintaining mechanical stability through proper material selection and process control
Solution Approach 2:
The patent employs composite material structures including low-k spacer materials combined with various dielectric layers (e.g., silicon oxide, silicon nitride, carbon-doped silicon nitride) to achieve both low parasitic capacitance and adequate mechanical support, creating a multi-layer composite system that balances electrical and mechanical requirements
2Object-generated harmful factors
If low-k materials are used for sidewall spacers, then parasitic capacitance is reduced, but mechanical weakness and depletion during processing occur
Solution Approach 1:
The patent uses composite material structures where low-k spacer materials are combined with supporting dielectric layers (silicon oxide, silicon nitride, carbon-doped silicon nitride) to provide mechanical reinforcement while maintaining the low parasitic capacitance property of the low-k material
Solution Approach 2:
The patent applies different material properties to different regions: the spacer core uses low-k material for electrical performance, while surrounding dielectric layers provide mechanical support, creating local quality differentiation that addresses both electrical and mechanical requirements simultaneously
3Object-generated harmful factors
If low-k materials are used for sidewall spacers, then parasitic capacitance is reduced, but depletion during processing steps occurs
Solution Approach 1:
The patent modifies the chemical composition parameters of the low-k spacer materials by incorporating carbon or boron doping, which reduces the materials' susceptibility to depletion during processing while maintaining their low dielectric constant property
Solution Approach 2:
The patent creates composite low-k materials combining silicon carbon nitride (SiCN) or silicon boron nitride (SiBN) with other dielectric components, achieving compositional stability during processing while preserving low parasitic capacitance characteristics
4Productivity
If densely packed transistors are formed, then circuit integration is improved, but parasitic capacitance from sidewall spacers increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the sidewall spacer material from high-k to low-k, directly reducing parasitic capacitance in densely packed transistor configurations and enabling higher circuit integration without proportionally increasing parasitic effects
Data Source
AI summary
One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.