Low-k Sidewall Spacer Transistor Fabrication
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Solution Overview
Problem
The existing fabrication processes for integrated circuits result in high parasitic capacitance due to the use of higher k dielectric materials for sidewall spacers, which affects the dynamic performance of transistor devices, and lower k dielectric materials are prone to damage during processing steps, losing their desired characteristics.
Innovation Solution
A process involving the formation of sacrificial sidewall spacers, epitaxial growth of raised source-drain regions, and replacement with a dielectric material having a dielectric constant less than 5 to create low-k sidewall spacers, using materials like silicon oxycarbonitride, silicon carbon oxide, or silicon carbon nitride, which are deposited using advanced techniques such as PEALD or ALD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher k dielectric materials are used for sidewall spacers, then structural integrity and processing stability are improved, but parasitic capacitance increases affecting dynamic performance
Solution Approach 1:
The patent changes the dielectric constant parameter from high-k (conventional) to low-k (less than 5) for the sidewall spacer material. This parameter change directly reduces parasitic capacitance between the gate and source/drain regions, improving transistor dynamic performance while maintaining adequate structural integrity through the specific low-k material composition and deposition process
Solution Approach 2:
The patent employs composite material structures including the low-k dielectric sidewall spacer combined with sacrificial spacers and specific deposition layers. The low-k material is integrated into the existing transistor structure alongside conventional high-k gate dielectric and metal gate electrodes, creating a composite device that achieves both structural reliability and reduced parasitic capacitance
2Object-generated harmful factors
If lower k dielectric materials are used for sidewall spacers, then parasitic capacitance is reduced improving dynamic performance, but the materials are prone to damage during processing steps
Solution Approach 1:
The patent applies preliminary protective actions by using sacrificial sidewall spacers that are formed first to define the spacer region, then low-k dielectric material is deposited conformally, and finally the sacrificial spacers are removed. This sequence protects the low-k material from direct exposure to harsh processing conditions that would otherwise damage it, while still achieving the low parasitic capacitance benefit
Solution Approach 2:
The sacrificial sidewall spacers act as intermediary structures that enable the introduction of low-k dielectric material without exposing it directly to damaging processing steps. The sacrificial spacers are removed after serving their protective and defining function, leaving the stable low-k material in the final structure with reduced parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and maintains the low-k dielectric characteristic, improving the dynamic performance of transistor devices while withstanding processing temperatures and steps.
Implementation Method 1
depositing a layer of a second dielectric material having a second dielectric constant less than the first dielectric constant in said openings and on side walls of the gate stack to form low-k sidewall spacers
Implementation Method 2
deposited using advanced techniques such as PEALD or ALD
Implementation Method 3
epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers
Data Source
AI summary
A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.