Low-k Isolation Structure for Stacked Transistor Capacitance

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Solution Overview

Problem

Conventional isolation regions in transistor devices have high dielectric constants, leading to undesirably high capacitance and affecting device performance.

Innovation Solution

Incorporation of a middle and bottom isolation region with an inner portion having a lower dielectric constant than silicon nitride and silicon boron carbonitride, such as silicon oxide or a vacancy, to reduce capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional isolation regions with high dielectric constant (silicon nitride or silicon boron carbonitride) are used, then isolation strength is improved, but capacitance increases undesirably

Engineering Contradiction:
Improveisolation strengthVSAvoidcapacitance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The isolation region is segmented into multiple layers with different dielectric constants. The first insulating material layer provides high dielectric constant for isolation strength, while the second insulating material layer with lower dielectric constant reduces capacitance. This segmentation allows simultaneous achievement of both isolation strength and low capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The isolation region uses a composite structure combining two different insulating materials. The first insulating material (e.g., silicon nitride or silicon boron carbonitride) provides strong isolation, while the second insulating material (e.g., silicon oxide) with lower dielectric constant reduces capacitance. This composite approach resolves the contradiction between isolation strength and capacitance.

Inventive Principle:
Principle #40Composite materials

2Device complexity

If single-layer isolation structure is used, then device complexity is reduced, but capacitance control is insufficient

Engineering Contradiction:
Improveisolation structure complexityVSAvoidcapacitance control
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The isolation structure is divided into two distinct insulating material layers deposited in sequence. The first layer provides baseline isolation with moderate capacitance, while the second layer with lower dielectric constant provides capacitance reduction. This segmentation enables better capacitance control while maintaining manageable device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric constant parameter is changed by introducing a second insulating material layer with lower dielectric constant than the first layer. This parameter change allows optimization of capacitance while maintaining the isolation function, resolving the contradiction between structural simplicity and capacitance control.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces capacitance and enhances the performance of transistor devices by using a multi-layer isolation structure with a lower dielectric constant.

Implementation Method 1

The second insulating material may have a lower dielectric constant than the first insulating material

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250254974A1Transistor device having low dielectric constant isolation region, and fabrication method thereof
Publication Date: 2025.08.07 SAMSUNG ELECTRONICS CO LTD
  • US20250254974A1 patent drawing
  • US20250254974A1 patent drawing
  • US20250254974A1 patent drawing

AI summary

Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes an isolation region that separates the upper transistor from the lower transistor. The isolation region has a dielectric constant that is lower than that of silicon nitride and lower than that of silicon boron carbonitride. Related methods of forming transistor devices are also provided.