Low-k Interconnect Via Formation for Finer Semiconductor Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires improved integration and electrical properties, which is challenging due to the need for finer patterns with narrower widths and smaller separation distances.
Innovation Solution
A method of manufacturing semiconductor devices involves forming interconnection lines buried in a first interlayer insulating layer, followed by the selective formation of a preliminary low dielectric constant layer containing silicon. This layer is then treated with ultraviolet (UV) and ozone (O3) to form a low dielectric constant layer, which is covered by an etch stop layer and a second interlayer insulating layer. Vias are formed to connect the interconnection lines, with a shape that bends along the upper and side surfaces of the low dielectric constant layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If patterns with finer width and smaller separation distance are implemented to increase integration degree, then device integration and electrical properties are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
A preliminary low dielectric constant layer is formed on the interlayer insulating layer before via formation. This preliminary layer serves as a sacrificial structure that is selectively removed to create via openings, enabling precise via positioning and shape control without requiring complex lithography and etching processes for fine patterns
Solution Approach 2:
The preliminary low dielectric constant layer acts as an intermediary structure between the interlayer insulating layer and the final via structure. It provides a temporary platform that facilitates via formation with bent shapes along the upper and side surfaces, simplifying the manufacturing of fine patterns while maintaining manufacturing precision
2Reliability
If via shape is bent along upper and side surfaces of low dielectric constant layer to improve separation distance, then electrical properties are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The via structure automatically forms a bent shape along the upper and side surfaces of the low dielectric constant layer through the formation process itself. The via conformally follows the contour of the preliminary layer, eliminating the need for complex post-processing to achieve the desired bent shape for improved electrical properties
Solution Approach 2:
The via shape is controlled by changing the formation parameters and sequence rather than by direct geometric specification. By controlling the removal of the preliminary low dielectric constant layer and subsequent material deposition, the via naturally adopts a bent configuration that enhances electrical properties while managing manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the degree of integration and electrical properties of semiconductor devices by allowing for finer patterns and improved separation distances between interconnection lines, while also simplifying the manufacturing process and reducing surface roughness.
Implementation Method 1
forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer
Data Source
AI summary
A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.