Low-k Interlayer Wiring Patterning With Protective Etch Openings
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Solution Overview
Problem
As the integration degree of dynamic random-access memory (DRAM) devices increases, the decreasing distances between wirings pose a challenge in effectively forming multiple wirings, and existing methods like EUV photolithography require expensive equipment and can damage low-k dielectric materials during the etching process.
Innovation Solution
A method involving multiple etching processes with protective patterns to form openings in an insulating interlayer, using ArF photolithography, which reduces damage to the low-k dielectric material and allows for precise spacing of wirings by forming first and second openings with different widths and depths, enhancing the insulative characteristics of the interlayer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV photolithography is used to form wirings with decreasing distances, then wiring spacing precision is improved, but equipment cost and process complexity increase
Solution Approach 1:
The patent segments the wiring formation process into multiple etching steps (first etching process and second etching process) instead of using a single complex EUV photolithography step. This allows the formation of wirings with precise spacing using conventional equipment by dividing the pattern formation into sequential stages with different mask patterns.
Solution Approach 2:
The patent applies preliminary action by forming a first mask pattern before the second mask pattern, where the first mask pattern defines initial wiring regions that guide subsequent etching. This preliminary structuring enables precise final wiring spacing through the second etching process without requiring advanced EUV equipment.
2Device complexity
If conventional etching processes are used to form wirings, then equipment cost is reduced, but damage to low-k dielectric material increases
Solution Approach 1:
The patent forms a protection pattern on the bottom and side surfaces of openings before performing the second etching process. This protection pattern acts as a buffer that absorbs etching damage and prevents direct contact between the etching process and the low-k dielectric material, thereby reducing material damage while using conventional etching equipment.
Solution Approach 2:
The protection pattern serves as an intermediary layer between the etching process and the low-k dielectric material. It mediates the interaction by providing a sacrificial barrier that protects the sensitive dielectric material from direct etching damage while still allowing the etching process to proceed effectively.
3Manufacturing precision
If multiple etching processes are performed to form precisely spaced wirings, then wiring spacing precision is improved, but process time increases
Solution Approach 1:
The patent merges multiple functions into the protection pattern formation step, where a single coating and etching process simultaneously creates the protection pattern and defines the final wiring openings. This consolidation reduces the total number of separate process steps compared to forming each wiring opening independently, thereby reducing overall process time while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms wirings with improved insulative characteristics by minimizing damage to the low-k dielectric material and allowing for precise spacing, thereby enhancing the reliability and efficiency of wiring formation in high-integration DRAM devices.
Implementation Method 1
The first etching mask may be removed by an ashing process
Implementation Method 2
The second etching mask may be removed by an ashing process
Data Source
AI summary
In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.