Low-k Word Line Capping Layer for DRAM Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of dynamic random access memory (DRAM) devices leads to increased parasitic capacitance and leakage current, degrading performance due to charge sharing effects and gate induced drain leakage (GIDL) current, which affects signal margin.
Innovation Solution
A memory structure is designed with a low dielectric constant material for the capping layer of the word line structure, reducing bit line parasitic capacitance and lowering GIDL current through the use of materials like silicon oxide and polysilicon, and optionally incorporating an air gap to further reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration of memory device increases, then memory capacity improves, but parasitic capacitance and leakage current increase
Solution Approach 1:
The patent changes the dielectric constant parameter of the capping layer material from conventional high-k materials to low-k materials (dielectric constant less than silicon nitride), which directly reduces parasitic capacitance and GIDL current while maintaining memory capacity
Solution Approach 2:
The patent employs composite material structures including low-k capping layer materials combined with specific word line materials (tungsten, polysilicon) and gate dielectric layers to achieve both high capacity and low parasitic effects
2Reliability
If bit line parasitic capacitance is reduced, then signal margin improves, but device structure complexity increases
Solution Approach 1:
The patent applies local quality by specifically modifying the capping layer material property (dielectric constant) in the critical region adjacent to the bit line contact, while maintaining conventional structures in other regions, thus reducing parasitic capacitance without overall structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances signal margin by minimizing parasitic capacitance and leakage current, thereby improving the operational performance of DRAM devices.
Implementation Method 1
The capping layer includes a first material film, and a dielectric constant of the first material film is smaller than a dielectric constant of silicon nitride
Implementation Method 2
The gate dielectric layer is disposed between the word line and the substrate
Data Source
AI summary
A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.