Low Latency Bypass Buffer for Data Transaction Requests
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Solution Overview
Problem
Existing buffering systems for data transaction requests face challenges in managing low latency and non-low latency requests efficiently, leading to potential starvation of non-low latency requests and inefficient bandwidth utilization, while requiring low circuit overhead and power consumption.
Innovation Solution
A buffering system with shared buffer circuitry, low latency identifying circuitry, output selection circuitry, rate detection circuitry, and bypass control circuitry that switches between bypass and non-bypass modes based on the output rate of low latency requests, ensuring minimum bandwidth for low latency requests and maximum latency for non-low latency requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If low latency data transaction requests are given priority in buffering, then low latency requests are serviced with minimal delay, but non-low latency requests may become starved of processing
Solution Approach 1:
The buffering system dynamically switches between bypass mode and non-bypass mode based on the detected output rate of low latency requests. When the output rate is below the threshold, bypass mode prioritizes low latency requests; when above the threshold, non-bypass mode ensures fair processing of all requests, preventing starvation while maintaining low latency performance.
Solution Approach 2:
The rate detection circuitry continuously monitors the output rate of low latency requests and provides feedback to the bypass control circuitry. This feedback mechanism enables the system to automatically adjust its operation mode based on real-time conditions, balancing priority treatment of low latency requests with fair service to non-low latency requests.
2Loss of time
If separate queues are used for low latency and non-low latency requests, then latency requirements are met, but device complexity increases
Solution Approach 1:
The patent merges both low latency and non-low latency requests into a single shared buffer queue, eliminating the need for separate queues. The output selection circuitry then intelligently determines which request to output based on the current operation mode (bypass or non-bypass), achieving latency handling without the complexity of multiple queues.
Solution Approach 2:
The shared buffer circuitry serves multiple functions by storing both low latency and non-low latency requests in the same structure. The output selection circuitry provides universal handling capability, adapting its behavior based on the detected output rate to prioritize appropriately while maintaining a simple unified buffer architecture.
3Productivity
If bypass mode is always used to prioritize low latency requests, then bandwidth for low latency requests is guaranteed, but non-low latency requests experience excessive blocking
Solution Approach 1:
The system dynamically adjusts its behavior based on real-time conditions. When the output rate of low latency requests is low (below threshold), bypass mode guarantees bandwidth priority. When the output rate is high (above threshold), the system switches to non-bypass mode to prevent excessive blocking of non-low latency requests, thus dynamically balancing bandwidth allocation and processing fairness.
Solution Approach 2:
The system changes its operational parameters (mode of operation) based on the detected output rate parameter. By monitoring the output rate and comparing it to a threshold, the system adjusts its prioritization behavior, switching between bypass and non-bypass modes to optimize both low latency performance and overall system fairness.
Data Source
AI summary
Buffer circuitry 14 is provided with shared buffer circuitry 20 which stores, in order of reception time, data transaction requests received from one or more data transaction sources. The buffer circuitry 14 operates in either a bypass mode or a non-bypass mode. When operating in the bypass mode, any low latency data transaction requests stored within the shared buffer circuitry are selected in order for output in preference to data transaction requests that are not low latency data transaction requests. In the non-bypass mode, transactions (whether or not they are low latency transactions) are output from the shared buffer circuitry 20 in accordance with the order in which they are received into the shared buffer circuitry 20. The switch between the bypass mode and the non-bypass mode is made in dependence upon comparison of a detected rate of output of low latency data transaction requests compared to a threshold value. If the rate exceeds the threshold value, then the switch is made to the non-bypass mode so that data transaction requests which are not low latency data transaction requests are permitted a fair share of the output bandwidth.