Low Latency Interrupt Collector for Peripheral Device Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The availability of general purpose inputs and outputs (I/O) on a processor limits the number of peripheral devices that can be interfaced with electronic devices, increasing cost and potentially leading to unacceptable interrupt latency in mobile electronics.
Innovation Solution
A low latency interrupt collector (LLIC) system that reduces the number of processor general purpose I/Os required to service multiple peripheral devices by using a few general purpose inputs and outputs to collect and communicate interrupt requests, allowing additional peripheral devices to interface without significantly increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If general purpose I/O are used to service peripheral device interrupts, then interrupt latency is reduced, but the number of available peripheral devices is limited and system cost increases
Solution Approach 1:
An interrupt collector is introduced as an intermediary component between peripheral devices and the processor. The collector receives interrupt requests from multiple peripheral devices and communicates their status to the processor through a limited number of general purpose I/O lines, enabling multiple peripherals to share the same I/O resources without increasing latency significantly
Solution Approach 2:
The interrupt collector serves multiple functions: it collects interrupt requests from numerous peripheral devices, prioritizes them based on configured policies, and communicates their status to the processor through a small set of shared I/O lines. This multi-functional approach allows a single collector to manage many peripherals using minimal I/O resources
2Loss of time
If general purpose I/O are dedicated to receiving peripheral device interrupts, then interrupt response is fast, but system cost increases
Solution Approach 1:
Multiple interrupt collection functions are merged into a single interrupt collector component. The collector consolidates interrupt requests from many peripheral devices and transmits their status through a small number of shared general purpose I/O lines, reducing the total number of I/O lines needed while maintaining fast interrupt response through efficient prioritization and polling mechanisms
3Device complexity
If communication bus polling is used to service peripheral devices, then number of general purpose I/O is reduced, but interrupt latency becomes unpredictable and unacceptable
Solution Approach 1:
The interrupt collector continuously monitors the interrupt status of multiple peripheral devices in advance and proactively communicates their status to the processor before actual interrupt service is needed. This preliminary action allows the processor to be prepared for incoming interrupts, reducing latency compared to reactive polling while using minimal I/O lines
Data Source
AI summary
This document provides apparatus and methods for providing low latency response from a processor to the interrupts collected from peripheral devices. In an example, an apparatus can collect interrupt requests from a plurality of peripheral devices, and can communicate interrupt information to a processor. Certain examples can reduce the quantity of processor general purpose inputs and outputs configured to receive the peripheral device interrupts in comparison to systems where the peripheral device interrupts are directly coupled to the processor.