Low-Latency Logical Unit With SRAM Mapping for Memory Swap
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Solution Overview
Problem
Existing memory systems lack efficient methods to manage system swap operations, leading to increased latency and reduced performance, particularly in high-processing applications like AI, AR, VR, and gaming, due to undefined parameters and inefficient data transfer between volatile and non-volatile memory.
Innovation Solution
Implementing a low latency logical unit (L3A) with a defined storage area and L2P table management using SRAM for mapping, combined with dedicated SLC blocks, to optimize system swap operations and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If system swap operations use conventional memory management methods, then data storage capacity is sufficient, but latency increases and performance decreases
Solution Approach 1:
The patent segments the memory system into distinct functional units: a low-latency logical unit (L3A) for system swap operations and other logical units for different functions. This segmentation allows swap operations to be handled by a specialized unit optimized for speed, while other operations use appropriate memory types, thereby reducing overall latency without compromising productivity.
Solution Approach 2:
The patent introduces an intermediary L3A logical unit that acts as a buffer between volatile memory (DRAM) and non-volatile memory (NAND). This intermediary handles system swap operations with optimized parameters including overprovisioning, SLC block allocation, and SRAM-based L2P tables, mediating the data transfer to reduce latency while maintaining productivity.
2Productivity
If undefined parameters are used in memory management, then system flexibility is maintained, but data transfer efficiency decreases
Solution Approach 1:
The patent applies parameter changes by defining specific optimized parameters for the L3A logical unit including overprovisioning ratios, SLC block allocation, SRAM L2P table configuration, and voltage thresholds. These defined parameters optimize data transfer efficiency for system swap operations while the modular structure manages complexity by confining parameter definitions to specific logical units.
3Reliability
If volatile memory is used for system swap, then access speed is fast, but data persistence and reliability are reduced
Solution Approach 1:
The patent implements preliminary action by pre-configuring the L3A logical unit with overprovisioned capacity, dedicated SLC blocks, and SRAM-based L2P tables before system swap operations occur. This preliminary setup ensures that when swap operations are needed, data can be quickly transferred to a persistent storage location that is already optimized and ready, thereby maintaining both reliability and speed.
Data Source
AI summary
Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.