Low-Latency External Memory Interface with Adjustable Latency Circuitry
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Solution Overview
Problem
Designing an external memory interface for integrated circuits that supports multiple source synchronous memory standards while minimizing latency and facilitating robust timing closure is challenging due to board skews and delay variations, which affect data transfer efficiency.
Innovation Solution
The implementation of a low-latency external memory interface with adjustable circuitry, including FIFO units and phase selection units, that allows for latency adjustments and rate conversions to synchronize data transfer across different memory standards, ensuring reliable data capture and minimizing command and data path latencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large data bus is divided into groups with separate clocks or strobes for each group, then reliable data capture despite board skew and delay variation is achieved, but device complexity and latency increase
Solution Approach 1:
The patent divides the data bus into groups of bits, with each group having its own clock or strobe signal. This segmentation allows independent timing control for each group, enabling reliable data capture despite board skew and delay variations while maintaining manageable complexity through structured organization
Solution Approach 2:
The external memory interface is designed to support multiple source synchronous memory standards (RLDRAM, QDR, DDR) through a unified architecture. The interface can be configured to work with different standards by adjusting parameters such as data bus width, clocking scheme, and strobe behavior, eliminating the need for separate dedicated interfaces for each standard
2Adaptability or versatility
If an external memory interface supports multiple memory interface standards, then adaptability is improved, but device complexity and design changes required increase
Solution Approach 1:
The patent implements a universal external memory interface that can operate with multiple source synchronous memory standards including RLDRAM, QDR, and DDR. The interface uses configurable parameters such as data bus width (e.g., 16-bit, 32-bit), clocking schemes (single clock, dual clock, strobe-based), and memory timing parameters to adapt to different standards without requiring separate dedicated interfaces for each standard
Solution Approach 2:
The interface supports multiple memory standards by allowing dynamic configuration of operational parameters including data bus width, clock frequency, strobe timing, and memory cycle timing. These parameter changes enable the same hardware interface to be adapted to different memory standards through software or hardware configuration rather than physical redesign
3Productivity
If command, read, and write data path latencies are minimized, then system performance is improved, but timing closure robustness decreases
Solution Approach 1:
The patent implements dynamic latency adjustment capabilities in the external memory interface, allowing the system to optimize command, read, and write data path latencies based on specific operational requirements. The interface can dynamically adjust timing parameters such as read latency, write latency, and command latency to balance performance optimization with timing closure robustness under different operating conditions
Data Source
AI summary
An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)−1] cycles of latency of the second rate.